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lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.h
changeset 103:9b9cfc5855e0
prev100:995e42e96cc9
next108:565de331ccec
author nkeynes
date Mon Mar 13 12:39:07 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change More rendering work in progress. Almost there now...
file annotate diff log raw
1.1 --- a/src/pvr2/pvr2.h Wed Feb 15 13:11:50 2006 +0000
1.2 +++ b/src/pvr2/pvr2.h Mon Mar 13 12:39:07 2006 +0000
1.3 @@ -1,7 +1,7 @@
1.4 /**
1.5 - * $Id: pvr2.h,v 1.8 2006-02-15 13:11:46 nkeynes Exp $
1.6 + * $Id: pvr2.h,v 1.9 2006-03-13 12:39:07 nkeynes Exp $
1.7 *
1.8 - * PVR2 (video chip) MMIO registers and functions.
1.9 + * PVR2 (video chip) functions and macros.
1.10 *
1.11 * Copyright (c) 2005 Nathan Keynes.
1.12 *
1.13 @@ -16,67 +16,12 @@
1.14 * GNU General Public License for more details.
1.15 */
1.16
1.17 -#include "mmio.h"
1.18 +#include "dream.h"
1.19 +#include "mem.h"
1.20 +#include "video.h"
1.21 +#include "pvr2/pvr2mmio.h"
1.22 +#include <GL/gl.h>
1.23
1.24 -MMIO_REGION_BEGIN( 0x005F8000, PVR2, "Power VR/2" )
1.25 - LONG_PORT( 0x000, PVRID, PORT_MR, 0x17FD11DB, "PVR2 Core ID" )
1.26 - LONG_PORT( 0x004, PVRVER, PORT_MR, 0x00000011, "PVR2 Core Version" )
1.27 - LONG_PORT( 0x008, PVRRST, PORT_MR, 0, "PVR2 Reset" )
1.28 - LONG_PORT( 0x014, RENDSTART, PORT_W, 0, "Start render" )
1.29 - LONG_PORT( 0x020, OBJBASE, PORT_MRW, 0, "Object buffer base offset" )
1.30 - LONG_PORT( 0x02C, TILEBASE, PORT_MRW, 0, "Tile buffer base offset" )
1.31 - LONG_PORT( 0x040, DISPBORDER, PORT_MRW, 0, "Border Colour (RGB)" )
1.32 - LONG_PORT( 0x044, DISPMODE, PORT_MRW, 0, "Display Mode" )
1.33 - LONG_PORT( 0x048, RENDMODE, PORT_MRW, 0, "Rendering Mode" )
1.34 - LONG_PORT( 0x04C, RENDSIZE, PORT_MRW, 0, "Rendering width (bytes/2)" )
1.35 - LONG_PORT( 0x050, DISPADDR1, PORT_MRW, 0, "Video memory base 1" )
1.36 - LONG_PORT( 0x054, DISPADDR2, PORT_MRW, 0, "Video memory base 2" )
1.37 - LONG_PORT( 0x05C, DISPSIZE, PORT_MRW, 0, "Display size" )
1.38 - LONG_PORT( 0x060, RENDADDR1, PORT_MRW, 0, "Rendering memory base 1" )
1.39 - LONG_PORT( 0x064, RENDADDR2, PORT_MRW, 0, "Rendering memory base 2" )
1.40 - LONG_PORT( 0x068, HCLIP, PORT_MRW, 0, "Horizontal clipping area" )
1.41 - LONG_PORT( 0x06C, VCLIP, PORT_MRW, 0, "Vertical clipping area" )
1.42 - LONG_PORT( 0x074, SHADOW, PORT_MRW, 0, "Shadowing" )
1.43 - LONG_PORT( 0x078, OBJCLIP, PORT_MRW, 0, "Object clip distance (float32)" )
1.44 - LONG_PORT( 0x084, TSPCLIP, PORT_MRW, 0, "Texture clip distance (float32)" )
1.45 - LONG_PORT( 0x088, BGPLANEZ, PORT_MRW, 0, "Background plane depth (float32)" )
1.46 - LONG_PORT( 0x08C, BGPLANECFG, PORT_MRW, 0, "Background plane config" )
1.47 - LONG_PORT( 0x0B0, FGTBLCOL, PORT_MRW, 0, "Fog table colour" )
1.48 - LONG_PORT( 0x0B4, FGVRTCOL, PORT_MRW, 0, "Fog vertex colour" )
1.49 - LONG_PORT( 0x0B8, FGCOEFF, PORT_MRW, 0, "Fog density coefficient (float16)" )
1.50 - LONG_PORT( 0x0BC, CLAMPHI, PORT_MRW, 0, "Clamp high colour" )
1.51 - LONG_PORT( 0x0C0, CLAMPLO, PORT_MRW, 0, "Clamp low colour" )
1.52 - LONG_PORT( 0x0C4, GUNPOS, PORT_MRW, 0, "Lightgun position" )
1.53 - LONG_PORT( 0x0CC, EVTPOS, PORT_MRW, 0, "Raster event position" )
1.54 - LONG_PORT( 0x0D0, VIDCFG, PORT_MRW, 0, "Sync configuration & enable" )
1.55 - LONG_PORT( 0x0D4, HBORDER, PORT_MRW, 0, "Horizontal border area" )
1.56 - LONG_PORT( 0x0D8, REFRESH, PORT_MRW, 0, "Refresh rates?" )
1.57 - LONG_PORT( 0x0DC, VBORDER, PORT_MRW, 0, "Vertical border area" )
1.58 - LONG_PORT( 0x0E0, SYNCPOS, PORT_MRW, 0, "Sync pulse timing" )
1.59 - LONG_PORT( 0x0E4, TSPCFG, PORT_MRW, 0, "Texture modulo width" )
1.60 - LONG_PORT( 0x0E8, VIDCFG2, PORT_MRW, 0, "Video configuration 2" )
1.61 - LONG_PORT( 0x0F0, VPOS, PORT_MRW, 0, "Vertical display position" )
1.62 - LONG_PORT( 0x0F4, SCALERCFG, PORT_MRW, 0, "Scaler configuration (?)" )
1.63 - LONG_PORT( 0x10C, BEAMPOS, PORT_R, 0, "Raster beam position" )
1.64 - LONG_PORT( 0x124, TAOPBST, PORT_MRW, 0, "TA Object Pointer Buffer start" )
1.65 - LONG_PORT( 0x128, TAOBST, PORT_MRW, 0, "TA Object Buffer start" )
1.66 - LONG_PORT( 0x12C, TAOPBEN, PORT_MRW, 0, "TA Object Pointer Buffer end" )
1.67 - LONG_PORT( 0x130, TAOBEN, PORT_MRW, 0, "TA Object Buffer end" )
1.68 - LONG_PORT( 0x134, TAOPBPOS, PORT_MRW, 0, "TA Object Pointer Buffer position" )
1.69 - LONG_PORT( 0x138, TAOBPOS, PORT_MRW, 0, "TA Object Buffer position" )
1.70 - LONG_PORT( 0x13C, TATBSZ, PORT_MRW, 0, "TA Tile Buffer size" )
1.71 - LONG_PORT( 0x140, TAOPBCFG, PORT_MRW, 0, "TA Object Pointer Buffer config" )
1.72 - LONG_PORT( 0x144, TAINIT, PORT_MRW, 0, "TA Initialize" )
1.73 - LONG_PORT( 0x164, TAOPLST, PORT_MRW, 0, "TA Object Pointer List start" )
1.74 -MMIO_REGION_END
1.75 -
1.76 -MMIO_REGION_BEGIN( 0x005F9000, PVR2PAL, "Power VR/2 CLUT Palettes" )
1.77 - LONG_PORT( 0x000, PAL0_0, PORT_MRW, 0, "Pal0 colour 0" )
1.78 -MMIO_REGION_END
1.79 -
1.80 -MMIO_REGION_BEGIN( 0x10000000, PVR2TA, "Power VR/2 TA Command port" )
1.81 - LONG_PORT( 0x000, TACMD, PORT_MRW, 0, "TA Command port" )
1.82 -MMIO_REGION_END
1.83
1.84 #define DISPMODE_DE 0x00000001 /* Display enable */
1.85 #define DISPMODE_SD 0x00000002 /* Scan double */
1.86 @@ -92,26 +37,136 @@
1.87 #define DISPSIZE_LPF 0x000FFC00 /* lines per field */
1.88 #define DISPSIZE_PPL 0x000003FF /* pixel words (32 bit) per line */
1.89
1.90 -#define VIDCFG_VP 0x00000001 /* V-sync polarity */
1.91 -#define VIDCFG_HP 0x00000002 /* H-sync polarity */
1.92 -#define VIDCFG_I 0x00000010 /* Interlace enable */
1.93 -#define VIDCFG_BS 0x000000C0 /* Broadcast standard */
1.94 -#define VIDCFG_VO 0x00000100 /* Video output enable */
1.95 +#define DISPCFG_VP 0x00000001 /* V-sync polarity */
1.96 +#define DISPCFG_HP 0x00000002 /* H-sync polarity */
1.97 +#define DISPCFG_I 0x00000010 /* Interlace enable */
1.98 +#define DISPCFG_BS 0x000000C0 /* Broadcast standard */
1.99 +#define DISPCFG_VO 0x00000100 /* Video output enable */
1.100
1.101 #define BS_NTSC 0x00000000
1.102 #define BS_PAL 0x00000040
1.103 #define BS_PALM 0x00000080 /* ? */
1.104 #define BS_PALN 0x000000C0 /* ? */
1.105
1.106 +#define PVR2_RAM_BASE 0x05000000
1.107 +#define PVR2_RAM_BASE_INT 0x04000000
1.108 +#define PVR2_RAM_SIZE (8 * 1024 * 1024)
1.109 +#define PVR2_RAM_PAGES (PVR2_RAM_SIZE>>12)
1.110 +
1.111 void pvr2_next_frame( void );
1.112 void pvr2_set_base_address( uint32_t );
1.113
1.114 +#define PVR2_CMD_END_OF_LIST 0x00
1.115 +#define PVR2_CMD_USER_CLIP 0x20
1.116 +#define PVR2_CMD_POLY_OPAQUE 0x80
1.117 +#define PVR2_CMD_MOD_OPAQUE 0x81
1.118 +#define PVR2_CMD_POLY_TRANS 0x82
1.119 +#define PVR2_CMD_MOD_TRANS 0x83
1.120 +#define PVR2_CMD_POLY_PUNCHOUT 0x84
1.121 +#define PVR2_CMD_VERTEX 0xE0
1.122 +#define PVR2_CMD_VERTEX_LAST 0xF0
1.123 +
1.124 +#define PVR2_POLY_TEXTURED 0x00000008
1.125 +#define PVR2_POLY_SPECULAR 0x00000004
1.126 +#define PVR2_POLY_SHADED 0x00000002
1.127 +#define PVR2_POLY_UV_16BIT 0x00000001
1.128 +
1.129 +#define PVR2_TEX_FORMAT_ARGB1555 0x00000000
1.130 +#define PVR2_TEX_FORMAT_RGB565 0x08000000
1.131 +#define PVR2_TEX_FORMAT_ARGB4444 0x10000000
1.132 +#define PVR2_TEX_FORMAT_YUV422 0x18000000
1.133 +#define PVR2_TEX_FORMAT_BUMPMAP 0x20000000
1.134 +#define PVR2_TEX_FORMAT_IDX4 0x28000000
1.135 +#define PVR2_TEX_FORMAT_IDX8 0x30000000
1.136 +
1.137 +#define PVR2_TEX_MIPMAP 0x80000000
1.138 +#define PVR2_TEX_COMPRESSED 0x40000000
1.139 +#define PVR2_TEX_FORMAT_MASK 0x38000000
1.140 +#define PVR2_TEX_UNTWIDDLED 0x04000000
1.141 +
1.142 +#define PVR2_TEX_ADDR(x) ( ((x)&0x1FFFFF)<<3 );
1.143 +#define PVR2_TEX_IS_MIPMAPPED(x) ( (x) & PVR2_TEX_MIPMAP )
1.144 +#define PVR2_TEX_IS_COMPRESSED(x) ( (x) & PVR2_TEX_COMPRESSED )
1.145 +#define PVR2_TEX_IS_TWIDDLED(x) (((x) & PVR2_TEX_UNTWIDDLED) == 0)
1.146 +
1.147 +extern video_driver_t video_driver;
1.148 +
1.149 +/****************************** Frame Buffer *****************************/
1.150 +
1.151 +/**
1.152 + * Write to the interleaved memory address space (aka 64-bit address space).
1.153 + */
1.154 +void pvr2_vram64_write( sh4addr_t dest, char *src, uint32_t length );
1.155 +
1.156 +/**
1.157 + * Read from the interleaved memory address space (aka 64-bit address space)
1.158 + */
1.159 +void pvr2_vram64_read( char *dest, sh4addr_t src, uint32_t length );
1.160 +
1.161 +/**************************** Tile Accelerator ***************************/
1.162 /**
1.163 * Process the data in the supplied buffer as an array of TA command lists.
1.164 * Any excess bytes are held pending until a complete list is sent
1.165 */
1.166 void pvr2_ta_write( char *buf, uint32_t length );
1.167
1.168 -void pvr2_init( void );
1.169
1.170 +/**
1.171 + * (Re)initialize the tile accelerator in preparation for the next scene.
1.172 + * Normally called immediately before commencing polygon transmission.
1.173 + */
1.174 +void pvr2_ta_init( void );
1.175 +
1.176 +/********************************* Renderer ******************************/
1.177 +
1.178 +/**
1.179 + * Initialize the rendering pipeline.
1.180 + * @return TRUE on success, FALSE on failure.
1.181 + */
1.182 +gboolean pvr2_render_init( void );
1.183 +
1.184 +/**
1.185 + * Render the current scene stored in PVR ram to the GL back buffer.
1.186 + */
1.187 void pvr2_render_scene( void );
1.188 +
1.189 +/**
1.190 + * Display the scene rendered to the supplied address.
1.191 + * @return TRUE if there was an available render that was displayed,
1.192 + * otherwise FALSE (and no action was taken)
1.193 + */
1.194 +gboolean pvr2_render_display_frame( uint32_t address );
1.195 +
1.196 +/****************************** Texture Cache ****************************/
1.197 +
1.198 +/**
1.199 + * Initialize the texture cache. Note that the GL context must have been
1.200 + * initialized before calling this function.
1.201 + */
1.202 +void texcache_init( void );
1.203 +
1.204 +
1.205 +/**
1.206 + * Flush all textures and delete. The cache will be non-functional until
1.207 + * the next call to texcache_init(). This would typically be done if
1.208 + * switching GL targets.
1.209 + */
1.210 +void texcache_shutdown( void );
1.211 +
1.212 +/**
1.213 + * Evict all textures contained in the page identified by a texture address.
1.214 + */
1.215 +void texcache_invalidate_page( uint32_t texture_addr );
1.216 +
1.217 +/**
1.218 + * Return a texture ID for the texture specified at the supplied address
1.219 + * and given parameters (the same sequence of bytes could in theory have
1.220 + * multiple interpretations). We use the texture address as the primary
1.221 + * index, but allow for multiple instances at each address. The texture
1.222 + * will be bound to the GL_TEXTURE_2D target before being returned.
1.223 + *
1.224 + * If the texture has already been bound, return the ID to which it was
1.225 + * bound. Otherwise obtain an unused texture ID and set it up appropriately.
1.226 + */
1.227 +GLuint texcache_get_texture( uint32_t texture_addr, int width, int height,
1.228 + int mode );
.