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tree revision 19:9da7a8e38f9d
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filename src/sh4/sh4mmio.c
changeset 19:9da7a8e38f9d
prev10:c898b37506e0
next23:1ec3acd0594d
author nkeynes
date Thu Dec 22 07:38:12 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Implement 95% of the SCIF serial interface
Implement basic load_bin_file function to try to load demos directly
Update TMU to run all 3 timers, start on general timing
file annotate diff log raw 
     1.1 --- a/src/sh4/sh4mmio.c	Sun Dec 11 05:15:36 2005 +0000

     1.2 +++ b/src/sh4/sh4mmio.c	Thu Dec 22 07:38:12 2005 +0000

     1.3 @@ -1,5 +1,6 @@

     1.4  #include "dream.h"

     1.5  #include "mem.h"

     1.6 +#include "clock.h"

     1.7  #include "sh4core.h"

     1.8  #include "sh4mmio.h"

     1.9  #define MMIO_IMPL

    1.10 @@ -30,7 +31,7 @@

    1.11  

    1.12  void mmu_init() 

    1.13  {

    1.14 -  cache = mem_alloc_pages(2);

    1.15 +    cache = mem_alloc_pages(2);

    1.16  }

    1.17  

    1.18  void mmu_set_cache_mode( int mode )

    1.19 @@ -135,6 +136,11 @@

    1.20  

    1.21  /********************************* CPG *************************************/

    1.22  

    1.23 +uint32_t sh4_freq = SH4_BASE_RATE;

    1.24 +uint32_t sh4_bus_freq = SH4_BASE_RATE;

    1.25 +uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;

    1.26 +

    1.27 +

    1.28  MMIO_REGION_STUBFNS( CPG )

    1.29  

    1.30  /********************************* DMAC *************************************/

    1.31 @@ -182,7 +188,7 @@

    1.32  {

    1.33      int tcr = MMIO_READ( TMU, TSTR );

    1.34      cycles *= 16;

    1.35 -    if( tcr & 1 ) {

    1.36 +    if( tcr & 0x01 ) {

    1.37          int count = cycles / timer_divider[0];

    1.38          int *val = MMIO_REG( TMU, TCNT0 );

    1.39          if( *val < count ) {

    1.40 @@ -194,13 +200,33 @@

    1.41              *val -= count;

    1.42          }

    1.43      }

    1.44 +    if( tcr & 0x02 ) {

    1.45 +        int count = cycles / timer_divider[1];

    1.46 +        int *val = MMIO_REG( TMU, TCNT1 );

    1.47 +        if( *val < count ) {

    1.48 +            MMIO_READ( TMU, TCR1 ) |= 0x100;

    1.49 +            /* interrupt goes here */

    1.50 +            count -= *val;

    1.51 +            *val = MMIO_READ( TMU, TCOR1 ) - count;

    1.52 +        } else {

    1.53 +            *val -= count;

    1.54 +        }

    1.55 +    }

    1.56 +    if( tcr & 0x04 ) {

    1.57 +        int count = cycles / timer_divider[2];

    1.58 +        int *val = MMIO_REG( TMU, TCNT2 );

    1.59 +        if( *val < count ) {

    1.60 +            MMIO_READ( TMU, TCR2 ) |= 0x100;

    1.61 +            /* interrupt goes here */

    1.62 +            count -= *val;

    1.63 +            *val = MMIO_READ( TMU, TCOR2 ) - count;

    1.64 +        } else {

    1.65 +            *val -= count;

    1.66 +        }

    1.67 +    }

    1.68  }

    1.69  

    1.70  /********************************** SCI *************************************/

    1.71  

    1.72  MMIO_REGION_STUBFNS( SCI )

    1.73  

    1.74 -/********************************* SCIF *************************************/

    1.75 -

    1.76 -MMIO_REGION_STUBFNS( SCIF )

    1.77 -
.