filename | src/sh4/sh4core.c |
changeset | 626:a010e30a30e9 |
prev | 617:476a717a54f3 |
next | 641:afb9a42c61c6 |
author | nkeynes |
date | Fri Feb 08 00:06:56 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Fix LDS/STS to FPUL/FPSCR to check the FPU disabled bit. Fixes the linux 2.4.0-test8 kernel boot (this wasn't exactly very well documented in the original manual) |
file | annotate | diff | log | raw |
1.1 --- a/src/sh4/sh4core.c Tue Jan 29 10:39:56 2008 +00001.2 +++ b/src/sh4/sh4core.c Fri Feb 08 00:06:56 2008 +00001.3 @@ -482,12 +482,14 @@1.4 case 0x5:1.5 { /* STS FPUL, Rn */1.6 uint32_t Rn = ((ir>>8)&0xF);1.7 + CHECKFPUEN();1.8 sh4r.r[Rn] = sh4r.fpul;1.9 }1.10 break;1.11 case 0x6:1.12 { /* STS FPSCR, Rn */1.13 uint32_t Rn = ((ir>>8)&0xF);1.14 + CHECKFPUEN();1.15 sh4r.r[Rn] = sh4r.fpscr;1.16 }1.17 break;1.18 @@ -913,6 +915,7 @@1.19 case 0x5:1.20 { /* STS.L FPUL, @-Rn */1.21 uint32_t Rn = ((ir>>8)&0xF);1.22 + CHECKFPUEN();1.23 CHECKWALIGN32( sh4r.r[Rn] );1.24 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );1.25 sh4r.r[Rn] -= 4;1.26 @@ -921,6 +924,7 @@1.27 case 0x6:1.28 { /* STS.L FPSCR, @-Rn */1.29 uint32_t Rn = ((ir>>8)&0xF);1.30 + CHECKFPUEN();1.31 CHECKWALIGN32( sh4r.r[Rn] );1.32 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );1.33 sh4r.r[Rn] -= 4;1.34 @@ -1100,6 +1104,7 @@1.35 case 0x5:1.36 { /* LDS.L @Rm+, FPUL */1.37 uint32_t Rm = ((ir>>8)&0xF);1.38 + CHECKFPUEN();1.39 CHECKRALIGN32( sh4r.r[Rm] );1.40 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);1.41 sh4r.r[Rm] +=4;1.42 @@ -1108,6 +1113,7 @@1.43 case 0x6:1.44 { /* LDS.L @Rm+, FPSCR */1.45 uint32_t Rm = ((ir>>8)&0xF);1.46 + CHECKFPUEN();1.47 CHECKRALIGN32( sh4r.r[Rm] );1.48 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);1.49 sh4r.r[Rm] +=4;1.50 @@ -1276,12 +1282,14 @@1.51 case 0x5:1.52 { /* LDS Rm, FPUL */1.53 uint32_t Rm = ((ir>>8)&0xF);1.54 + CHECKFPUEN();1.55 sh4r.fpul = sh4r.r[Rm];1.56 }1.57 break;1.58 case 0x6:1.59 { /* LDS Rm, FPSCR */1.60 uint32_t Rm = ((ir>>8)&0xF);1.61 + CHECKFPUEN();1.62 sh4r.fpscr = sh4r.r[Rm];1.63 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];1.64 }
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