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lxdream.org :: lxdream/src/aica/armmem.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/aica/armmem.c
changeset 736:a02d1475ccfd
prev561:533f6b478071
next811:7ff871670e58
author nkeynes
date Mon Jul 14 07:44:42 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Re-indent everything consistently
Fix include guards for consistency as well
file annotate diff log raw
1.1 --- a/src/aica/armmem.c Tue Jan 01 05:08:38 2008 +0000
1.2 +++ b/src/aica/armmem.c Mon Jul 14 07:44:42 2008 +0000
1.3 @@ -31,35 +31,35 @@
1.4
1.5 int arm_has_page( uint32_t addr ) {
1.6 return ( addr < 0x00200000 ||
1.7 - (addr >= 0x00800000 && addr <= 0x00805000 ) );
1.8 + (addr >= 0x00800000 && addr <= 0x00805000 ) );
1.9 }
1.10
1.11 uint32_t arm_read_long( uint32_t addr ) {
1.12 if( addr < 0x00200000 ) {
1.13 - return *(int32_t *)(arm_mem + addr);
1.14 - /* Main sound ram */
1.15 + return *(int32_t *)(arm_mem + addr);
1.16 + /* Main sound ram */
1.17 } else {
1.18 - uint32_t val;
1.19 - switch( addr & 0xFFFFF000 ) {
1.20 - case 0x00800000:
1.21 - val = mmio_region_AICA0_read(addr&0x0FFF);
1.22 - // DEBUG( "ARM long read from %08X => %08X", addr, val );
1.23 - return val;
1.24 - case 0x00801000:
1.25 - val = mmio_region_AICA1_read(addr&0x0FFF);
1.26 - // DEBUG( "ARM long read from %08X => %08X", addr, val );
1.27 - return val;
1.28 - case 0x00802000:
1.29 - val = mmio_region_AICA2_read(addr&0x0FFF);
1.30 - // DEBUG( "ARM long read from %08X => %08X", addr, val );
1.31 - return val;
1.32 - case 0x00803000:
1.33 - case 0x00804000:
1.34 - return *(int32_t *)(arm_mem_scratch + addr - 0x00803000);
1.35 - }
1.36 + uint32_t val;
1.37 + switch( addr & 0xFFFFF000 ) {
1.38 + case 0x00800000:
1.39 + val = mmio_region_AICA0_read(addr&0x0FFF);
1.40 + // DEBUG( "ARM long read from %08X => %08X", addr, val );
1.41 + return val;
1.42 + case 0x00801000:
1.43 + val = mmio_region_AICA1_read(addr&0x0FFF);
1.44 + // DEBUG( "ARM long read from %08X => %08X", addr, val );
1.45 + return val;
1.46 + case 0x00802000:
1.47 + val = mmio_region_AICA2_read(addr&0x0FFF);
1.48 + // DEBUG( "ARM long read from %08X => %08X", addr, val );
1.49 + return val;
1.50 + case 0x00803000:
1.51 + case 0x00804000:
1.52 + return *(int32_t *)(arm_mem_scratch + addr - 0x00803000);
1.53 + }
1.54 }
1.55 ERROR( "Attempted long read to undefined page: %08X",
1.56 - addr );
1.57 + addr );
1.58 /* Undefined memory */
1.59 return 0;
1.60 }
1.61 @@ -75,31 +75,31 @@
1.62 void arm_write_long( uint32_t addr, uint32_t value )
1.63 {
1.64 if( addr < 0x00200000 ) {
1.65 - /* Main sound ram */
1.66 - *(uint32_t *)(arm_mem + addr) = value;
1.67 + /* Main sound ram */
1.68 + *(uint32_t *)(arm_mem + addr) = value;
1.69 } else {
1.70 - switch( addr & 0xFFFFF000 ) {
1.71 - case 0x00800000:
1.72 - // DEBUG( "ARM long write to %08X <= %08X", addr, value );
1.73 - mmio_region_AICA0_write(addr&0x0FFF, value);
1.74 - break;
1.75 - case 0x00801000:
1.76 - // DEBUG( "ARM long write to %08X <= %08X", addr, value );
1.77 - mmio_region_AICA1_write(addr&0x0FFF, value);
1.78 - break;
1.79 - case 0x00802000:
1.80 - // DEBUG( "ARM long write to %08X <= %08X", addr, value );
1.81 - mmio_region_AICA2_write(addr&0x0FFF, value);
1.82 - break;
1.83 - case 0x00803000:
1.84 - case 0x00804000:
1.85 - *(uint32_t *)(arm_mem_scratch + addr - 0x00803000) = value;
1.86 - break;
1.87 - default:
1.88 - ERROR( "Attempted long write to undefined address: %08X",
1.89 - addr );
1.90 - /* Undefined memory */
1.91 - }
1.92 + switch( addr & 0xFFFFF000 ) {
1.93 + case 0x00800000:
1.94 + // DEBUG( "ARM long write to %08X <= %08X", addr, value );
1.95 + mmio_region_AICA0_write(addr&0x0FFF, value);
1.96 + break;
1.97 + case 0x00801000:
1.98 + // DEBUG( "ARM long write to %08X <= %08X", addr, value );
1.99 + mmio_region_AICA1_write(addr&0x0FFF, value);
1.100 + break;
1.101 + case 0x00802000:
1.102 + // DEBUG( "ARM long write to %08X <= %08X", addr, value );
1.103 + mmio_region_AICA2_write(addr&0x0FFF, value);
1.104 + break;
1.105 + case 0x00803000:
1.106 + case 0x00804000:
1.107 + *(uint32_t *)(arm_mem_scratch + addr - 0x00803000) = value;
1.108 + break;
1.109 + default:
1.110 + ERROR( "Attempted long write to undefined address: %08X",
1.111 + addr );
1.112 + /* Undefined memory */
1.113 + }
1.114 }
1.115 return;
1.116 }
1.117 @@ -108,50 +108,50 @@
1.118 {
1.119 switch( addr & 0x03 ) {
1.120 case 0:
1.121 - return (val & 0xFFFFFF00) | byte;
1.122 + return (val & 0xFFFFFF00) | byte;
1.123 case 1:
1.124 - return (val & 0xFFFF00FF) | (byte<<8);
1.125 + return (val & 0xFFFF00FF) | (byte<<8);
1.126 case 2:
1.127 - return (val & 0xFF00FFFF) | (byte<<16);
1.128 + return (val & 0xFF00FFFF) | (byte<<16);
1.129 case 3:
1.130 - return (val & 0x00FFFFFF) | (byte<<24);
1.131 + return (val & 0x00FFFFFF) | (byte<<24);
1.132 default:
1.133 - return val; // Can't happen, but make gcc happy
1.134 + return val; // Can't happen, but make gcc happy
1.135 }
1.136 }
1.137
1.138 void arm_write_byte( uint32_t addr, uint32_t value )
1.139 {
1.140 if( addr < 0x00200000 ) {
1.141 - /* Main sound ram */
1.142 - *(uint8_t *)(arm_mem + addr) = (uint8_t)value;
1.143 + /* Main sound ram */
1.144 + *(uint8_t *)(arm_mem + addr) = (uint8_t)value;
1.145 } else {
1.146 - uint32_t tmp;
1.147 - switch( addr & 0xFFFFF000 ) {
1.148 - case 0x00800000:
1.149 - tmp = MMIO_READ( AICA0, addr & 0x0FFC );
1.150 - value = arm_combine_byte( addr, tmp, value );
1.151 - mmio_region_AICA0_write(addr&0x0FFC, value);
1.152 - break;
1.153 - case 0x00801000:
1.154 - tmp = MMIO_READ( AICA1, addr & 0x0FFC );
1.155 - value = arm_combine_byte( addr, tmp, value );
1.156 - mmio_region_AICA1_write(addr&0x0FFC, value);
1.157 - break;
1.158 - case 0x00802000:
1.159 - tmp = MMIO_READ( AICA2, addr & 0x0FFC );
1.160 - value = arm_combine_byte( addr, tmp, value );
1.161 - mmio_region_AICA2_write(addr&0x0FFC, value);
1.162 - break;
1.163 - case 0x00803000:
1.164 - case 0x00804000:
1.165 - *(uint8_t *)(arm_mem_scratch + addr - 0x00803000) = (uint8_t)value;
1.166 - break;
1.167 - default:
1.168 - ERROR( "Attempted byte write to undefined address: %08X",
1.169 - addr );
1.170 - /* Undefined memory */
1.171 - }
1.172 + uint32_t tmp;
1.173 + switch( addr & 0xFFFFF000 ) {
1.174 + case 0x00800000:
1.175 + tmp = MMIO_READ( AICA0, addr & 0x0FFC );
1.176 + value = arm_combine_byte( addr, tmp, value );
1.177 + mmio_region_AICA0_write(addr&0x0FFC, value);
1.178 + break;
1.179 + case 0x00801000:
1.180 + tmp = MMIO_READ( AICA1, addr & 0x0FFC );
1.181 + value = arm_combine_byte( addr, tmp, value );
1.182 + mmio_region_AICA1_write(addr&0x0FFC, value);
1.183 + break;
1.184 + case 0x00802000:
1.185 + tmp = MMIO_READ( AICA2, addr & 0x0FFC );
1.186 + value = arm_combine_byte( addr, tmp, value );
1.187 + mmio_region_AICA2_write(addr&0x0FFC, value);
1.188 + break;
1.189 + case 0x00803000:
1.190 + case 0x00804000:
1.191 + *(uint8_t *)(arm_mem_scratch + addr - 0x00803000) = (uint8_t)value;
1.192 + break;
1.193 + default:
1.194 + ERROR( "Attempted byte write to undefined address: %08X",
1.195 + addr );
1.196 + /* Undefined memory */
1.197 + }
1.198 }
1.199 return;
1.200 }
.