Search
lxdream.org :: lxdream/src/sh4/scif.c :: diff
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/scif.c
changeset 736:a02d1475ccfd
prev561:533f6b478071
next828:b42865f00fb5
author nkeynes
date Mon Jul 14 07:44:42 2008 +0000 (13 years ago)
permissions -rw-r--r--
last change Re-indent everything consistently
Fix include guards for consistency as well
file annotate diff log raw
1.1 --- a/src/sh4/scif.c Tue Jan 01 05:08:38 2008 +0000
1.2 +++ b/src/sh4/scif.c Mon Jul 14 07:44:42 2008 +0000
1.3 @@ -58,7 +58,7 @@
1.4 void serial_attach_device( serial_device_t dev )
1.5 {
1.6 if( serial_device != NULL )
1.7 - serial_detach_device();
1.8 + serial_detach_device();
1.9 serial_device = dev;
1.10 }
1.11
1.12 @@ -74,19 +74,19 @@
1.13 */
1.14 void serial_transmit_data( char *data, int length ) {
1.15 if( length == 0 )
1.16 - return;
1.17 + return;
1.18 serial_data_block_t block =
1.19 - g_malloc( sizeof( struct serial_data_block ) + length );
1.20 + g_malloc( sizeof( struct serial_data_block ) + length );
1.21 block->length = length;
1.22 block->offset = 0;
1.23 block->next = NULL;
1.24 memcpy( block->data, data, length );
1.25 -
1.26 +
1.27 if( serial_recvq_head == NULL ) {
1.28 - serial_recvq_head = serial_recvq_tail = block;
1.29 + serial_recvq_head = serial_recvq_tail = block;
1.30 } else {
1.31 - serial_recvq_tail->next = block;
1.32 - serial_recvq_tail = block;
1.33 + serial_recvq_tail->next = block;
1.34 + serial_recvq_tail = block;
1.35 }
1.36 }
1.37
1.38 @@ -95,15 +95,15 @@
1.39 */
1.40 static int serial_transmit_dequeue( ) {
1.41 if( serial_recvq_head != NULL ) {
1.42 - uint8_t val = serial_recvq_head->data[serial_recvq_head->offset++];
1.43 - if( serial_recvq_head->offset >= serial_recvq_head->length ) {
1.44 - serial_data_block_t next = serial_recvq_head->next;
1.45 - g_free( serial_recvq_head );
1.46 - serial_recvq_head = next;
1.47 - if( next == NULL )
1.48 - serial_recvq_tail = NULL;
1.49 - }
1.50 - return (int)(unsigned int)val;
1.51 + uint8_t val = serial_recvq_head->data[serial_recvq_head->offset++];
1.52 + if( serial_recvq_head->offset >= serial_recvq_head->length ) {
1.53 + serial_data_block_t next = serial_recvq_head->next;
1.54 + g_free( serial_recvq_head );
1.55 + serial_recvq_head = next;
1.56 + if( next == NULL )
1.57 + serial_recvq_tail = NULL;
1.58 + }
1.59 + return (int)(unsigned int)val;
1.60 }
1.61 return -1;
1.62
1.63 @@ -195,7 +195,7 @@
1.64 {
1.65 int val = SCIF_recvq.tail - SCIF_recvq.head;
1.66 if( val < 0 ) {
1.67 - val = FIFO_ARR_LENGTH - SCIF_recvq.head + SCIF_recvq.tail;
1.68 + val = FIFO_ARR_LENGTH - SCIF_recvq.head + SCIF_recvq.tail;
1.69 }
1.70 return val;
1.71 }
1.72 @@ -205,10 +205,10 @@
1.73 uint8_t result;
1.74 uint32_t tmp, length;
1.75 if( SCIF_recvq.head == SCIF_recvq.tail )
1.76 - return -1; /* No data */
1.77 + return -1; /* No data */
1.78 result = SCIF_recvq.data[SCIF_recvq.head++];
1.79 if( SCIF_recvq.head > FIFO_LENGTH )
1.80 - SCIF_recvq.head = 0;
1.81 + SCIF_recvq.head = 0;
1.82
1.83 /* Update data count register */
1.84 tmp = MMIO_READ( SCIF, SCFDR2 ) & 0xF0;
1.85 @@ -217,16 +217,16 @@
1.86
1.87 /* Clear flags (if requested ) */
1.88 if( clearFlags && length < SCIF_recvq.trigger ) {
1.89 - tmp = SCFSR2_RDF;
1.90 - if( length == 0 )
1.91 - tmp |= SCFSR2_DR;
1.92 - tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
1.93 - MMIO_WRITE( SCIF, SCFSR2, tmp );
1.94 - /* If both flags are cleared, clear the interrupt as well */
1.95 - if( (tmp & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() )
1.96 - intc_clear_interrupt( INT_SCIF_RXI );
1.97 + tmp = SCFSR2_RDF;
1.98 + if( length == 0 )
1.99 + tmp |= SCFSR2_DR;
1.100 + tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
1.101 + MMIO_WRITE( SCIF, SCFSR2, tmp );
1.102 + /* If both flags are cleared, clear the interrupt as well */
1.103 + if( (tmp & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() )
1.104 + intc_clear_interrupt( INT_SCIF_RXI );
1.105 }
1.106 -
1.107 +
1.108 return (int)(unsigned int)result;
1.109 }
1.110
1.111 @@ -235,13 +235,13 @@
1.112 uint32_t tmp, length;
1.113 int newpos = SCIF_recvq.tail + 1;
1.114 if( newpos > FIFO_LENGTH )
1.115 - newpos = 0;
1.116 + newpos = 0;
1.117 if( newpos == SCIF_recvq.head ) {
1.118 - /* FIFO full - set ORER and discard the value */
1.119 - MMIO_WRITE( SCIF, SCLSR2, SCLSR2_ORER );
1.120 - if( IS_RECEIVE_ERROR_IRQ_ENABLED() )
1.121 - intc_raise_interrupt( INT_SCIF_ERI );
1.122 - return FALSE;
1.123 + /* FIFO full - set ORER and discard the value */
1.124 + MMIO_WRITE( SCIF, SCLSR2, SCLSR2_ORER );
1.125 + if( IS_RECEIVE_ERROR_IRQ_ENABLED() )
1.126 + intc_raise_interrupt( INT_SCIF_ERI );
1.127 + return FALSE;
1.128 }
1.129 SCIF_recvq.data[SCIF_recvq.tail] = value;
1.130
1.131 @@ -253,9 +253,9 @@
1.132 /* Update status register */
1.133 tmp = MMIO_READ( SCIF, SCFSR2 );
1.134 if( length >= SCIF_recvq.trigger ) {
1.135 - tmp |= SCFSR2_RDF;
1.136 - if( IS_RECEIVE_IRQ_ENABLED() )
1.137 - intc_raise_interrupt( INT_SCIF_RXI );
1.138 + tmp |= SCFSR2_RDF;
1.139 + if( IS_RECEIVE_IRQ_ENABLED() )
1.140 + intc_raise_interrupt( INT_SCIF_RXI );
1.141 DMAC_trigger( DMAC_SCIF_RDF );
1.142 }
1.143 MMIO_WRITE( SCIF, SCFSR2, tmp );
1.144 @@ -274,14 +274,14 @@
1.145 MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0xF0 );
1.146 MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) & ~(SCFSR2_DR|SCFSR2_RDF) );
1.147 if( IS_RECEIVE_IRQ_ENABLED() )
1.148 - intc_clear_interrupt( INT_SCIF_RXI );
1.149 + intc_clear_interrupt( INT_SCIF_RXI );
1.150 }
1.151
1.152 static inline uint8_t SCIF_sendq_size( )
1.153 {
1.154 int val = SCIF_sendq.tail - SCIF_sendq.head;
1.155 if( val < 0 ) {
1.156 - val = FIFO_ARR_LENGTH - SCIF_sendq.head + SCIF_sendq.tail;
1.157 + val = FIFO_ARR_LENGTH - SCIF_sendq.head + SCIF_sendq.tail;
1.158 }
1.159 return val;
1.160 }
1.161 @@ -296,27 +296,27 @@
1.162 uint8_t result;
1.163 uint32_t tmp, length;
1.164 if( SCIF_sendq.head == SCIF_sendq.tail )
1.165 - return -1; /* No data */
1.166 + return -1; /* No data */
1.167
1.168 /* Update queue head pointer */
1.169 result = SCIF_sendq.data[SCIF_sendq.head++];
1.170 if( SCIF_sendq.head > FIFO_LENGTH )
1.171 - SCIF_sendq.head = 0;
1.172 + SCIF_sendq.head = 0;
1.173
1.174 /* Update data count register */
1.175 tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F;
1.176 length = SCIF_sendq_size();
1.177 MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) );
1.178 -
1.179 +
1.180 /* Update status register */
1.181 if( length <= SCIF_sendq.trigger ) {
1.182 - tmp = MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TDFE;
1.183 - if( length == 0 )
1.184 - tmp |= SCFSR2_TEND; /* Transmission ended - no data waiting */
1.185 - if( IS_TRANSMIT_IRQ_ENABLED() )
1.186 - intc_raise_interrupt( INT_SCIF_TXI );
1.187 + tmp = MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TDFE;
1.188 + if( length == 0 )
1.189 + tmp |= SCFSR2_TEND; /* Transmission ended - no data waiting */
1.190 + if( IS_TRANSMIT_IRQ_ENABLED() )
1.191 + intc_raise_interrupt( INT_SCIF_TXI );
1.192 DMAC_trigger( DMAC_SCIF_TDE );
1.193 - MMIO_WRITE( SCIF, SCFSR2, tmp );
1.194 + MMIO_WRITE( SCIF, SCFSR2, tmp );
1.195 }
1.196 return (int)(unsigned int)result;
1.197 }
1.198 @@ -337,10 +337,10 @@
1.199 uint32_t tmp, length;
1.200 int newpos = SCIF_sendq.tail + 1;
1.201 if( newpos > FIFO_LENGTH )
1.202 - newpos = 0;
1.203 + newpos = 0;
1.204 if( newpos == SCIF_sendq.head ) {
1.205 - /* FIFO full - discard */
1.206 - return FALSE;
1.207 + /* FIFO full - discard */
1.208 + return FALSE;
1.209 }
1.210 SCIF_sendq.data[SCIF_sendq.tail] = value;
1.211 SCIF_sendq.tail = newpos;
1.212 @@ -349,17 +349,17 @@
1.213 tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F;
1.214 length = SCIF_sendq_size();
1.215 MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) );
1.216 -
1.217 +
1.218 /* Update flags if requested */
1.219 if( clearFlags ) {
1.220 - tmp = SCFSR2_TEND;
1.221 - if( length > SCIF_sendq.trigger ) {
1.222 - tmp |= SCFSR2_TDFE;
1.223 - if( IS_TRANSMIT_IRQ_ENABLED() )
1.224 - intc_clear_interrupt( INT_SCIF_TXI );
1.225 - }
1.226 - tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
1.227 - MMIO_WRITE( SCIF, SCFSR2, tmp );
1.228 + tmp = SCFSR2_TEND;
1.229 + if( length > SCIF_sendq.trigger ) {
1.230 + tmp |= SCFSR2_TDFE;
1.231 + if( IS_TRANSMIT_IRQ_ENABLED() )
1.232 + intc_clear_interrupt( INT_SCIF_TXI );
1.233 + }
1.234 + tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
1.235 + MMIO_WRITE( SCIF, SCFSR2, tmp );
1.236 }
1.237 return TRUE;
1.238 }
1.239 @@ -370,7 +370,7 @@
1.240 MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0x0F );
1.241 MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TEND | SCFSR2_TDFE );
1.242 if( IS_TRANSMIT_IRQ_ENABLED() ) {
1.243 - intc_raise_interrupt( INT_SCIF_TXI );
1.244 + intc_raise_interrupt( INT_SCIF_TXI );
1.245 DMAC_trigger( DMAC_SCIF_TDE );
1.246 }
1.247 }
1.248 @@ -389,27 +389,27 @@
1.249 uint32_t recvq_size = SCIF_recvq_size();
1.250
1.251 if( sendq_size != 0 )
1.252 - result |= SCFSR2_TEND;
1.253 + result |= SCFSR2_TEND;
1.254
1.255 if( sendq_size <= SCIF_sendq.trigger )
1.256 - result |= SCFSR2_TDFE;
1.257 + result |= SCFSR2_TDFE;
1.258 else if( (result & SCFSR2_TDFE) == 0 && IS_TRANSMIT_IRQ_ENABLED() )
1.259 - intc_clear_interrupt( INT_SCIF_TXI );
1.260 + intc_clear_interrupt( INT_SCIF_TXI );
1.261
1.262 if( recvq_size >= SCIF_recvq.trigger )
1.263 - result |= SCFSR2_RDF;
1.264 + result |= SCFSR2_RDF;
1.265 if( (value & SCFSR2_DR) != 0 && (result & SCFSR2_DR) == 0 &&
1.266 - recvq_size != 0 )
1.267 - result |= SCFSR2_DR;
1.268 + recvq_size != 0 )
1.269 + result |= SCFSR2_DR;
1.270 if( (result & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() )
1.271 - intc_clear_interrupt( INT_SCIF_RXI );
1.272 + intc_clear_interrupt( INT_SCIF_RXI );
1.273
1.274 if( IS_RECEIVE_ERROR_IRQ_ENABLED() ) {
1.275 - if( (result & SCFSR2_BRK) == 0 )
1.276 - intc_clear_interrupt( INT_SCIF_BRI );
1.277 - if( (result & SCFSR2_ER) == 0 &&
1.278 - (MMIO_READ( SCIF, SCLSR2 ) & SCLSR2_ORER) == 0 )
1.279 - intc_clear_interrupt( INT_SCIF_ERI );
1.280 + if( (result & SCFSR2_BRK) == 0 )
1.281 + intc_clear_interrupt( INT_SCIF_BRI );
1.282 + if( (result & SCFSR2_ER) == 0 &&
1.283 + (MMIO_READ( SCIF, SCLSR2 ) & SCLSR2_ORER) == 0 )
1.284 + intc_clear_interrupt( INT_SCIF_ERI );
1.285 }
1.286 }
1.287
1.288 @@ -420,7 +420,7 @@
1.289 {
1.290 MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_BRK );
1.291 if( IS_RECEIVE_ERROR_IRQ_ENABLED() )
1.292 - intc_raise_interrupt( INT_SCIF_BRI );
1.293 + intc_raise_interrupt( INT_SCIF_BRI );
1.294 }
1.295
1.296 const static int SCIF_CLOCK_MULTIPLIER[4] = {1, 4, 16, 64};
1.297 @@ -436,22 +436,22 @@
1.298
1.299 } else {
1.300
1.301 - /* Otherwise, SH4 peripheral clock divided by n */
1.302 - int mult = SCIF_CLOCK_MULTIPLIER[MMIO_READ( SCIF, SCSMR2 ) & 0x03];
1.303 -
1.304 - /* Then process the bitrate register */
1.305 - int bbr = MMIO_READ( SCIF, SCBRR2 ) & 0xFF;
1.306 + /* Otherwise, SH4 peripheral clock divided by n */
1.307 + int mult = SCIF_CLOCK_MULTIPLIER[MMIO_READ( SCIF, SCSMR2 ) & 0x03];
1.308
1.309 - int baudrate = sh4_peripheral_freq / (32 * mult * (bbr+1) );
1.310 -
1.311 - if( serial_device != NULL && serial_device->set_line_speed != NULL )
1.312 - serial_device->set_line_speed( baudrate );
1.313 + /* Then process the bitrate register */
1.314 + int bbr = MMIO_READ( SCIF, SCBRR2 ) & 0xFF;
1.315
1.316 - SCIF_tick_period = sh4_peripheral_period * (32 * mult * (bbr+1));
1.317 + int baudrate = sh4_peripheral_freq / (32 * mult * (bbr+1) );
1.318
1.319 - /*
1.320 + if( serial_device != NULL && serial_device->set_line_speed != NULL )
1.321 + serial_device->set_line_speed( baudrate );
1.322 +
1.323 + SCIF_tick_period = sh4_peripheral_period * (32 * mult * (bbr+1));
1.324 +
1.325 + /*
1.326 clock_set_tick_rate( CLOCK_SCIF, baudrate / 10 );
1.327 - */
1.328 + */
1.329 }
1.330 }
1.331
1.332 @@ -459,9 +459,9 @@
1.333 {
1.334 switch( reg ) {
1.335 case SCFRDR2: /* Receive data */
1.336 - return SCIF_recvq_dequeue(FALSE);
1.337 + return SCIF_recvq_dequeue(FALSE);
1.338 default:
1.339 - return MMIO_READ( SCIF, reg );
1.340 + return MMIO_READ( SCIF, reg );
1.341 }
1.342 }
1.343
1.344 @@ -470,95 +470,95 @@
1.345 uint32_t tmp;
1.346 switch( reg ) {
1.347 case SCSMR2: /* Serial mode register */
1.348 - /* Bit 6 => 0 = 8-bit, 1 = 7-bit
1.349 - * Bit 5 => 0 = Parity disabled, 1 = parity enabled
1.350 - * Bit 4 => 0 = Even parity, 1 = Odd parity
1.351 - * Bit 3 => 0 = 1 stop bit, 1 = 2 stop bits
1.352 - * Bits 0-1 => Clock select 00 = P, 01 = P/4, 10 = P/16, 11 = P/64
1.353 - */
1.354 - val &= 0x007B;
1.355 - if( serial_device != NULL ) {
1.356 - serial_device->set_line_params( val );
1.357 - }
1.358 - tmp = MMIO_READ( SCIF, SCSMR2 );
1.359 - if( (tmp & 0x03) != (val & 0x03) ) {
1.360 - /* Clock change */
1.361 - SCIF_update_line_speed( );
1.362 - }
1.363 - /* Save for later read-back */
1.364 - MMIO_WRITE( SCIF, SCSMR2, val );
1.365 - break;
1.366 + /* Bit 6 => 0 = 8-bit, 1 = 7-bit
1.367 + * Bit 5 => 0 = Parity disabled, 1 = parity enabled
1.368 + * Bit 4 => 0 = Even parity, 1 = Odd parity
1.369 + * Bit 3 => 0 = 1 stop bit, 1 = 2 stop bits
1.370 + * Bits 0-1 => Clock select 00 = P, 01 = P/4, 10 = P/16, 11 = P/64
1.371 + */
1.372 + val &= 0x007B;
1.373 + if( serial_device != NULL ) {
1.374 + serial_device->set_line_params( val );
1.375 + }
1.376 + tmp = MMIO_READ( SCIF, SCSMR2 );
1.377 + if( (tmp & 0x03) != (val & 0x03) ) {
1.378 + /* Clock change */
1.379 + SCIF_update_line_speed( );
1.380 + }
1.381 + /* Save for later read-back */
1.382 + MMIO_WRITE( SCIF, SCSMR2, val );
1.383 + break;
1.384 case SCBRR2: /* Bit rate register */
1.385 - MMIO_WRITE( SCIF, SCBRR2, val );
1.386 - SCIF_update_line_speed( );
1.387 - break;
1.388 + MMIO_WRITE( SCIF, SCBRR2, val );
1.389 + SCIF_update_line_speed( );
1.390 + break;
1.391 case SCSCR2: /* Serial control register */
1.392 - /* Bit 7 => Transmit-FIFO-data-empty interrupt enabled
1.393 - * Bit 6 => Receive-data-full interrupt enabled
1.394 - * Bit 5 => Transmit enable
1.395 - * Bit 4 => Receive enable
1.396 - * Bit 3 => Receive-error/break interrupt enabled
1.397 - * Bit 1 => Clock enable
1.398 - */
1.399 - val &= 0x00FA;
1.400 - /* Clear any interrupts that just became disabled */
1.401 - if( (val & SCSCR2_TIE) == 0 )
1.402 - intc_clear_interrupt( INT_SCIF_TXI );
1.403 - if( (val & SCSCR2_RIE) == 0 )
1.404 - intc_clear_interrupt( INT_SCIF_RXI );
1.405 - if( (val & (SCSCR2_RIE|SCSCR2_REIE)) == 0 ) {
1.406 - intc_clear_interrupt( INT_SCIF_ERI );
1.407 - intc_clear_interrupt( INT_SCIF_BRI );
1.408 - }
1.409 -
1.410 - MMIO_WRITE( SCIF, reg, val );
1.411 - break;
1.412 + /* Bit 7 => Transmit-FIFO-data-empty interrupt enabled
1.413 + * Bit 6 => Receive-data-full interrupt enabled
1.414 + * Bit 5 => Transmit enable
1.415 + * Bit 4 => Receive enable
1.416 + * Bit 3 => Receive-error/break interrupt enabled
1.417 + * Bit 1 => Clock enable
1.418 + */
1.419 + val &= 0x00FA;
1.420 + /* Clear any interrupts that just became disabled */
1.421 + if( (val & SCSCR2_TIE) == 0 )
1.422 + intc_clear_interrupt( INT_SCIF_TXI );
1.423 + if( (val & SCSCR2_RIE) == 0 )
1.424 + intc_clear_interrupt( INT_SCIF_RXI );
1.425 + if( (val & (SCSCR2_RIE|SCSCR2_REIE)) == 0 ) {
1.426 + intc_clear_interrupt( INT_SCIF_ERI );
1.427 + intc_clear_interrupt( INT_SCIF_BRI );
1.428 + }
1.429 +
1.430 + MMIO_WRITE( SCIF, reg, val );
1.431 + break;
1.432 case SCFTDR2: /* Transmit FIFO data register */
1.433 - SCIF_sendq_enqueue( val, FALSE );
1.434 - break;
1.435 + SCIF_sendq_enqueue( val, FALSE );
1.436 + break;
1.437 case SCFSR2: /* Serial status register */
1.438 - /* Bits 12-15 Parity error count
1.439 - * Bits 8-11 Framing erro count
1.440 - * Bit 7 - Receive error
1.441 - * Bit 6 - Transmit end
1.442 - * Bit 5 - Transmit FIFO data empty
1.443 - * Bit 4 - Break detect
1.444 - * Bit 3 - Framing error
1.445 - * Bit 2 - Parity error
1.446 - * Bit 1 - Receive FIFO data full
1.447 - * Bit 0 - Receive data ready
1.448 - */
1.449 - /* Clear off any flags/interrupts that are being set to 0 */
1.450 - SCIF_update_status( val );
1.451 - break;
1.452 + /* Bits 12-15 Parity error count
1.453 + * Bits 8-11 Framing erro count
1.454 + * Bit 7 - Receive error
1.455 + * Bit 6 - Transmit end
1.456 + * Bit 5 - Transmit FIFO data empty
1.457 + * Bit 4 - Break detect
1.458 + * Bit 3 - Framing error
1.459 + * Bit 2 - Parity error
1.460 + * Bit 1 - Receive FIFO data full
1.461 + * Bit 0 - Receive data ready
1.462 + */
1.463 + /* Clear off any flags/interrupts that are being set to 0 */
1.464 + SCIF_update_status( val );
1.465 + break;
1.466 case SCFCR2: /* FIFO control register */
1.467 - val &= 0x0F;
1.468 - SCIF_recvq.trigger = SCIF_recvq_triggers[val >> 6];
1.469 - SCIF_sendq.trigger = SCIF_sendq_triggers[(val >> 4) & 0x03];
1.470 - if( val & SCFCR2_TFRST ) {
1.471 - SCIF_sendq_clear();
1.472 - }
1.473 - if( val & SCFCR2_RFRST ) {
1.474 - SCIF_recvq_clear();
1.475 - }
1.476 + val &= 0x0F;
1.477 + SCIF_recvq.trigger = SCIF_recvq_triggers[val >> 6];
1.478 + SCIF_sendq.trigger = SCIF_sendq_triggers[(val >> 4) & 0x03];
1.479 + if( val & SCFCR2_TFRST ) {
1.480 + SCIF_sendq_clear();
1.481 + }
1.482 + if( val & SCFCR2_RFRST ) {
1.483 + SCIF_recvq_clear();
1.484 + }
1.485
1.486 - MMIO_WRITE( SCIF, reg, val );
1.487 - break;
1.488 + MMIO_WRITE( SCIF, reg, val );
1.489 + break;
1.490 case SCSPTR2: /* Serial Port Register */
1.491 - MMIO_WRITE( SCIF, reg, val );
1.492 - /* NOT IMPLEMENTED */
1.493 - WARN( "SCSPTR2 not implemented: Write %08X", val );
1.494 - break;
1.495 + MMIO_WRITE( SCIF, reg, val );
1.496 + /* NOT IMPLEMENTED */
1.497 + WARN( "SCSPTR2 not implemented: Write %08X", val );
1.498 + break;
1.499 case SCLSR2:
1.500 - val = val & SCLSR2_ORER;
1.501 - if( val == 0 ) {
1.502 - MMIO_WRITE( SCIF, SCLSR2, val );
1.503 - if( (MMIO_READ( SCIF, SCFSR2 ) & SCFSR2_ER) == 0 &&
1.504 - IS_RECEIVE_ERROR_IRQ_ENABLED() )
1.505 - intc_clear_interrupt( INT_SCIF_ERI );
1.506 - }
1.507 -
1.508 - break;
1.509 + val = val & SCLSR2_ORER;
1.510 + if( val == 0 ) {
1.511 + MMIO_WRITE( SCIF, SCLSR2, val );
1.512 + if( (MMIO_READ( SCIF, SCFSR2 ) & SCFSR2_ER) == 0 &&
1.513 + IS_RECEIVE_ERROR_IRQ_ENABLED() )
1.514 + intc_clear_interrupt( INT_SCIF_ERI );
1.515 + }
1.516 +
1.517 + break;
1.518 }
1.519 }
1.520
1.521 @@ -579,42 +579,42 @@
1.522 gboolean rcvd = FALSE;
1.523
1.524 if( IS_LOOPBACK_ENABLED() ) {
1.525 - if( IS_TRANSMIT_ENABLED() ) {
1.526 - int val = SCIF_sendq_dequeue();
1.527 - if( val != -1 && IS_RECEIVE_ENABLED() ) {
1.528 - SCIF_recvq_enqueue( val );
1.529 - rcvd = TRUE;
1.530 - }
1.531 - }
1.532 + if( IS_TRANSMIT_ENABLED() ) {
1.533 + int val = SCIF_sendq_dequeue();
1.534 + if( val != -1 && IS_RECEIVE_ENABLED() ) {
1.535 + SCIF_recvq_enqueue( val );
1.536 + rcvd = TRUE;
1.537 + }
1.538 + }
1.539 } else {
1.540 - if( IS_TRANSMIT_ENABLED() ) {
1.541 - int val = SCIF_sendq_dequeue();
1.542 - if( val != -1 && serial_device != NULL &&
1.543 - serial_device->receive_data != NULL ) {
1.544 - serial_device->receive_data( val );
1.545 - }
1.546 - }
1.547 -
1.548 - if( IS_RECEIVE_ENABLED() ) {
1.549 - int val = serial_transmit_dequeue();
1.550 - if( val != -1 ) {
1.551 - SCIF_recvq_enqueue( val );
1.552 - rcvd = TRUE;
1.553 - }
1.554 - }
1.555 + if( IS_TRANSMIT_ENABLED() ) {
1.556 + int val = SCIF_sendq_dequeue();
1.557 + if( val != -1 && serial_device != NULL &&
1.558 + serial_device->receive_data != NULL ) {
1.559 + serial_device->receive_data( val );
1.560 + }
1.561 + }
1.562 +
1.563 + if( IS_RECEIVE_ENABLED() ) {
1.564 + int val = serial_transmit_dequeue();
1.565 + if( val != -1 ) {
1.566 + SCIF_recvq_enqueue( val );
1.567 + rcvd = TRUE;
1.568 + }
1.569 + }
1.570 }
1.571
1.572 /* Check if we need to set the DR flag */
1.573 if( !rcvd && !SCIF_rcvd_last_tick &&
1.574 - SCIF_recvq.head != SCIF_recvq.tail &&
1.575 - SCIF_recvq_size() < SCIF_recvq.trigger ) {
1.576 - uint32_t tmp = MMIO_READ( SCIF, SCFSR2 );
1.577 - if( (tmp & SCFSR2_DR) == 0 ) {
1.578 - MMIO_WRITE( SCIF, SCFSR2, tmp | SCFSR2_DR );
1.579 - if( IS_RECEIVE_IRQ_ENABLED() )
1.580 - intc_raise_interrupt( INT_SCIF_RXI );
1.581 - DMAC_trigger( DMAC_SCIF_RDF );
1.582 - }
1.583 + SCIF_recvq.head != SCIF_recvq.tail &&
1.584 + SCIF_recvq_size() < SCIF_recvq.trigger ) {
1.585 + uint32_t tmp = MMIO_READ( SCIF, SCFSR2 );
1.586 + if( (tmp & SCFSR2_DR) == 0 ) {
1.587 + MMIO_WRITE( SCIF, SCFSR2, tmp | SCFSR2_DR );
1.588 + if( IS_RECEIVE_IRQ_ENABLED() )
1.589 + intc_raise_interrupt( INT_SCIF_RXI );
1.590 + DMAC_trigger( DMAC_SCIF_RDF );
1.591 + }
1.592 }
1.593 SCIF_rcvd_last_tick = rcvd;
1.594 }
1.595 @@ -630,7 +630,7 @@
1.596 {
1.597 SCIF_tick_remainder += nanosecs;
1.598 while( SCIF_tick_remainder >= SCIF_tick_period ) {
1.599 - SCIF_tick_remainder -= SCIF_tick_period;
1.600 - SCIF_clock_tick();
1.601 + SCIF_tick_remainder -= SCIF_tick_period;
1.602 + SCIF_clock_tick();
1.603 }
1.604 }
.