1.1 --- a/src/sh4/sh4.h	Mon May 26 10:42:18 2008 +0000
     1.2 +++ b/src/sh4/sh4.h	Mon Jul 14 07:44:42 2008 +0000
     1.3 @@ -67,8 +67,8 @@
     1.4      uint32_t sr, pr, pc, fpscr;
     1.5      uint32_t t, m, q, s; /* really boolean - 0 or 1 */
     1.6      union {
     1.7 -	int32_t i;
     1.8 -	float f;
     1.9 +        int32_t i;
    1.10 +        float f;
    1.11      } fpul;
    1.12      uint32_t pad; // FIXME: remove in next DST version
    1.13      float fr[2][16];
    1.14 @@ -77,13 +77,13 @@
    1.15  
    1.16      uint32_t r_bank[8]; /* hidden banked registers */
    1.17      int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
    1.18 -    
    1.19 +
    1.20      uint32_t new_pc; /* Not a real register, but used to handle delay slots */
    1.21      uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
    1.22                               when no events are pending */
    1.23      uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
    1.24      int in_delay_slot; /* flag to indicate the current instruction is in
    1.25 -                             * a delay slot (certain rules apply) */
    1.26 +     * a delay slot (certain rules apply) */
    1.27      uint32_t slice_cycle; /* Current nanosecond within the timeslice */
    1.28      int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
    1.29  };