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tree revision 577:a181aeacd6e8 lxdream-mmu
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filename src/sh4/mmu.c
changeset 577:a181aeacd6e8
prev571:9bc09948d0f2
next583:ba995fadf173
author nkeynes
date Mon Jan 14 10:23:49 2008 +0000 (16 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Remove asm file and convert to inline (easier to cope with platform conventions)
Add breakpoint support
Add MMU store-queue support
file annotate diff log raw 
     1.1 --- a/src/sh4/mmu.c	Thu Jan 10 08:28:37 2008 +0000

     1.2 +++ b/src/sh4/mmu.c	Mon Jan 14 10:23:49 2008 +0000

     1.3 @@ -845,3 +845,50 @@

     1.4  	return TRUE;

     1.5      }

     1.6  }

     1.7 +

     1.8 +gboolean sh4_flush_store_queue( sh4addr_t addr )

     1.9 +{

    1.10 +    uint32_t mmucr = MMIO_READ(MMU,MMUCR);

    1.11 +    int queue = (addr&0x20)>>2;

    1.12 +    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];

    1.13 +    sh4addr_t target;

    1.14 +    /* Store queue operation */

    1.15 +    if( mmucr & MMUCR_AT ) {

    1.16 +	int entryNo;

    1.17 +	if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {

    1.18 +	    entryNo = mmu_utlb_lookup_vpn_asid( addr );

    1.19 +	} else {

    1.20 +	    entryNo = mmu_utlb_lookup_vpn( addr );

    1.21 +	}

    1.22 +	switch(entryNo) {

    1.23 +	case -1:

    1.24 +	    MMU_TLB_WRITE_MISS_ERROR(addr);

    1.25 +	    return FALSE;

    1.26 +	case -2:

    1.27 +	    MMU_TLB_MULTI_HIT_ERROR(addr);

    1.28 +	    return FALSE;

    1.29 +	default:

    1.30 +	    if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)

    1.31 +		: ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {

    1.32 +		/* protection violation */

    1.33 +		MMU_TLB_WRITE_PROT_ERROR(addr);

    1.34 +		return FALSE;

    1.35 +	    }

    1.36 +	    

    1.37 +	    if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {

    1.38 +		MMU_TLB_INITIAL_WRITE_ERROR(addr);

    1.39 +		return FALSE;

    1.40 +	    }

    1.41 +	    

    1.42 +	    /* finally generate the target address */

    1.43 +	    target = ((mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 

    1.44 +		      (addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;

    1.45 +	}

    1.46 +    } else {

    1.47 +	uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;

    1.48 +	target = (addr&0x03FFFFE0) | hi;

    1.49 +    }

    1.50 +    mem_copy_to_sh4( target, src, 32 );

    1.51 +    return TRUE;

    1.52 +}

    1.53 +
.