filename | src/sh4/sh4x86.in |
changeset | 577:a181aeacd6e8 |
prev | 571:9bc09948d0f2 |
next | 584:5c29dd7297df |
author | nkeynes |
date | Mon Jan 14 10:23:49 2008 +0000 (14 years ago) |
branch | lxdream-mmu |
permissions | -rw-r--r-- |
last change | Remove asm file and convert to inline (easier to cope with platform conventions) Add breakpoint support Add MMU store-queue support |
file | annotate | diff | log | raw |
1.1 --- a/src/sh4/sh4x86.in Thu Jan 10 08:28:37 2008 +00001.2 +++ b/src/sh4/sh4x86.in Mon Jan 14 10:23:49 2008 +00001.3 @@ -125,7 +125,7 @@1.4 xlat_recovery[xlat_recovery_posn].sh4_icount = (pc - sh4_x86.block_start_pc)>>1;1.5 xlat_recovery_posn++;1.6 }1.7 -1.8 +1.9 /**1.10 * Emit an instruction to load an SH4 reg into a real register1.11 */1.12 @@ -355,11 +355,18 @@1.13 #endif1.14 #endif1.16 +void sh4_translate_emit_breakpoint( sh4vma_t pc )1.17 +{1.18 + load_imm32( R_EAX, XLAT_EXIT_BREAKPOINT );1.19 + call_func1( sh4_translate_exit, R_EAX );1.20 +}1.21 +1.23 /**1.24 * Translate a single instruction. Delayed branches are handled specially1.25 * by translating both branch and delayed instruction as a single unit (as1.26 *1.27 + * The instruction MUST be in the icache (assert check)1.28 *1.29 * @return true if the instruction marks the end of a basic block1.30 * (eg a branch or1.31 @@ -367,12 +374,21 @@1.32 uint32_t sh4_translate_instruction( sh4addr_t pc )1.33 {1.34 uint32_t ir;1.35 - /* Read instruction */1.36 - if( IS_IN_ICACHE(pc) ) {1.37 - ir = *(uint16_t *)GET_ICACHE_PTR(pc);1.38 - } else {1.39 + /* Read instruction from icache */1.40 + assert( IS_IN_ICACHE(pc) );1.41 + ir = *(uint16_t *)GET_ICACHE_PTR(pc);1.42 +1.43 + /* PC is not in the current icache - this usually means we're running1.44 + * with MMU on, and we've gone past the end of the page. And since1.45 + * sh4_translate_block is pretty careful about this, it means we're1.46 + * almost certainly in a delay slot.1.47 + *1.48 + * Since we can't assume the page is present (and we can't fault it in1.49 + * at this point, inline a call to sh4_execute_instruction (with a few1.50 + * small repairs to cope with the different environment).1.51 + */1.52 ir = sh4_read_word(pc);1.53 - }1.54 +1.55 if( !sh4_x86.in_delay_slot ) {1.56 sh4_x86_add_recovery(pc);1.57 }1.58 @@ -2425,8 +2441,10 @@1.59 MOV_r32_r32( R_EAX, R_ECX );1.60 AND_imm32_r32( 0xFC000000, R_EAX );1.61 CMP_imm32_r32( 0xE0000000, R_EAX );1.62 - JNE_rel8(CALL_FUNC1_SIZE, end);1.63 + JNE_rel8(8+CALL_FUNC1_SIZE, end);1.64 call_func1( sh4_flush_store_queue, R_ECX );1.65 + TEST_r32_r32( R_EAX, R_EAX );1.66 + JE_exc(-1);1.67 JMP_TARGET(end);1.68 sh4_x86.tstate = TSTATE_NONE;1.69 :}
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