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lxdream.org :: lxdream/src/sh4/sh4mem.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mem.c
changeset 550:a27e31340147
prev527:14c9489f647e
next559:06714bc64271
next586:2a3ba82cf243
author nkeynes
date Thu Dec 06 10:43:30 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Add support for the MMIO side of the TLB (and LDTLB)
file annotate diff log raw
1.1 --- a/src/sh4/sh4mem.c Sun Nov 18 11:12:44 2007 +0000
1.2 +++ b/src/sh4/sh4mem.c Thu Dec 06 10:43:30 2007 +0000
1.3 @@ -17,6 +17,7 @@
1.4 */
1.5
1.6 #define MODULE sh4_module
1.7 +#define ENABLE_TRACE_IO 1
1.8
1.9 #include <string.h>
1.10 #include <zlib.h>
1.11 @@ -73,12 +74,23 @@
1.12 {
1.13 struct mmio_region *io = P4_io[(addr&0x1FFFFFFF)>>19];
1.14 if( !io ) {
1.15 - if( (addr & 0xFF000000) != 0xF4000000 ) {
1.16 - /* OC address cache isn't implemented, but don't complain about it.
1.17 - * Complain about anything else though */
1.18 - WARN( "Attempted read from unknown P4 region: %08X", addr );
1.19 + switch( addr & 0x1F000000 ) {
1.20 + case 0x00000000: case 0x01000000: case 0x02000000: case 0x03000000:
1.21 + /* Store queue - readable? */
1.22 + return 0;
1.23 + break;
1.24 + case 0x10000000: return mmu_icache_addr_read( addr );
1.25 + case 0x11000000: return mmu_icache_data_read( addr );
1.26 + case 0x12000000: return mmu_itlb_addr_read( addr );
1.27 + case 0x13000000: return mmu_itlb_data_read( addr );
1.28 + case 0x14000000: return mmu_ocache_addr_read( addr );
1.29 + case 0x15000000: return mmu_ocache_data_read( addr );
1.30 + case 0x16000000: return mmu_utlb_addr_read( addr );
1.31 + case 0x17000000: return mmu_utlb_data_read( addr );
1.32 + default:
1.33 + WARN( "Attempted read from unknown or invalid P4 region: %08X", addr );
1.34 + return 0;
1.35 }
1.36 - return 0;
1.37 } else {
1.38 int32_t val = io->io_read( addr&0xFFF );
1.39 TRACE_P4IO( "Long read %08X <= %08X", io, (addr&0xFFF), val, addr );
1.40 @@ -90,12 +102,20 @@
1.41 {
1.42 struct mmio_region *io = P4_io[(addr&0x1FFFFFFF)>>19];
1.43 if( !io ) {
1.44 - if( (addr & 0xFC000000) == 0xE0000000 ) {
1.45 + switch( addr & 0x1F000000 ) {
1.46 + case 0x00000000: case 0x01000000: case 0x02000000: case 0x03000000:
1.47 /* Store queue */
1.48 SH4_WRITE_STORE_QUEUE( addr, val );
1.49 - } else if( (addr & 0xFF000000) != 0xF4000000 ) {
1.50 - /* OC address cache isn't implemented, but don't complain about it.
1.51 - * Complain about anything else though */
1.52 + break;
1.53 + case 0x10000000: mmu_icache_addr_write( addr, val ); break;
1.54 + case 0x11000000: mmu_icache_data_write( addr, val ); break;
1.55 + case 0x12000000: mmu_itlb_addr_write( addr, val ); break;
1.56 + case 0x13000000: mmu_itlb_data_write( addr, val ); break;
1.57 + case 0x14000000: mmu_ocache_addr_write( addr, val ); break;
1.58 + case 0x15000000: mmu_ocache_data_write( addr, val ); break;
1.59 + case 0x16000000: mmu_utlb_addr_write( addr, val ); break;
1.60 + case 0x17000000: mmu_utlb_data_write( addr, val ); break;
1.61 + default:
1.62 WARN( "Attempted write to unknown P4 region: %08X", addr );
1.63 }
1.64 } else {
.