1.1 --- a/src/sh4/sh4mmio.c	Thu Nov 08 11:54:16 2007 +0000
     1.2 +++ b/src/sh4/sh4mmio.c	Thu Dec 06 10:43:30 2007 +0000
     1.3 @@ -28,81 +28,6 @@
     1.4  #define MMIO_IMPL
     1.5  #include "sh4/sh4mmio.h"
     1.6  
     1.7 -/********************************* MMU *************************************/
     1.8 -
     1.9 -MMIO_REGION_READ_DEFFN( MMU )
    1.10 -
    1.11 -#define OCRAM_START (0x1C000000>>PAGE_BITS)
    1.12 -#define OCRAM_END   (0x20000000>>PAGE_BITS)
    1.13 -
    1.14 -static sh4ptr_t cache = NULL;
    1.15 -
    1.16 -void mmio_region_MMU_write( uint32_t reg, uint32_t val )
    1.17 -{
    1.18 -    switch(reg) {
    1.19 -    case MMUCR:
    1.20 -	if( val & MMUCR_AT ) {
    1.21 -	    ERROR( "MMU Address translation not implemented!" );
    1.22 -	    dreamcast_stop();
    1.23 -	}
    1.24 -	break;
    1.25 -    case CCR:
    1.26 -	mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
    1.27 -	break;
    1.28 -    default:
    1.29 -	break;
    1.30 -    }
    1.31 -    MMIO_WRITE( MMU, reg, val );
    1.32 -}
    1.33 -
    1.34 -
    1.35 -void MMU_init() 
    1.36 -{
    1.37 -    cache = mem_alloc_pages(2);
    1.38 -}
    1.39 -
    1.40 -void MMU_reset()
    1.41 -{
    1.42 -    mmio_region_MMU_write( CCR, 0 );
    1.43 -}
    1.44 -
    1.45 -void MMU_save_state( FILE *f )
    1.46 -{
    1.47 -    fwrite( cache, 4096, 2, f );
    1.48 -}
    1.49 -
    1.50 -int MMU_load_state( FILE *f )
    1.51 -{
    1.52 -    /* Setup the cache mode according to the saved register value
    1.53 -     * (mem_load runs before this point to load all MMIO data)
    1.54 -     */
    1.55 -    mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
    1.56 -    if( fread( cache, 4096, 2, f ) != 2 ) {
    1.57 -	return 1;
    1.58 -    }
    1.59 -    return 0;
    1.60 -}
    1.61 -
    1.62 -void mmu_set_cache_mode( int mode )
    1.63 -{
    1.64 -    uint32_t i;
    1.65 -    switch( mode ) {
    1.66 -        case MEM_OC_INDEX0: /* OIX=0 */
    1.67 -            for( i=OCRAM_START; i<OCRAM_END; i++ )
    1.68 -                page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
    1.69 -            break;
    1.70 -        case MEM_OC_INDEX1: /* OIX=1 */
    1.71 -            for( i=OCRAM_START; i<OCRAM_END; i++ )
    1.72 -                page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
    1.73 -            break;
    1.74 -        default: /* disabled */
    1.75 -            for( i=OCRAM_START; i<OCRAM_END; i++ )
    1.76 -                page_map[i] = NULL;
    1.77 -            break;
    1.78 -    }
    1.79 -}
    1.80 -
    1.81 -
    1.82  /********************************* BSC *************************************/
    1.83  
    1.84  uint32_t bsc_input = 0x0300;