Search
lxdream.org :: lxdream/src/sh4/sh4mmio.h :: diff
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4mmio.h
changeset 550:a27e31340147
prev30:89b30313d757
next561:533f6b478071
author nkeynes
date Thu Dec 06 10:43:30 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Add support for the MMIO side of the TLB (and LDTLB)
file annotate diff log raw
1.1 --- a/src/sh4/sh4mmio.h Sun Dec 25 05:57:00 2005 +0000
1.2 +++ b/src/sh4/sh4mmio.h Thu Dec 06 10:43:30 2007 +0000
1.3 @@ -17,6 +17,7 @@
1.4 * GNU General Public License for more details.
1.5 */
1.6
1.7 +#include "lxdream.h"
1.8 #include "mmio.h"
1.9
1.10 #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \
1.11 @@ -35,8 +36,8 @@
1.12 LONG_PORT( 0x008, TTB, PORT_MRW, UNDEFINED, "Translation table base" )
1.13 LONG_PORT( 0x00C, TEA, PORT_MRW, UNDEFINED, "TLB exception address" )
1.14 LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" )
1.15 - BYTE_PORT( 0x14, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
1.16 - BYTE_PORT( 0x18, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
1.17 + BYTE_PORT( 0x014, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
1.18 + BYTE_PORT( 0x018, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
1.19 LONG_PORT( 0x01C, CCR, PORT_MRW, 0, "Cache control register" )
1.20 LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" )
1.21 LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
1.22 @@ -208,7 +209,25 @@
1.23 #define MEM_OC_INDEX0 CCR_ORA
1.24 #define MEM_OC_INDEX1 CCR_ORA|CCR_OIX
1.25
1.26 +/* MMU functions */
1.27 void mmu_init(void);
1.28 void mmu_set_cache_mode( int );
1.29 +void mmu_ldtlb(void);
1.30
1.31 +int32_t mmu_icache_addr_read( sh4addr_t addr );
1.32 +int32_t mmu_icache_data_read( sh4addr_t addr );
1.33 +int32_t mmu_itlb_addr_read( sh4addr_t addr );
1.34 +int32_t mmu_itlb_data_read( sh4addr_t addr );
1.35 +int32_t mmu_ocache_addr_read( sh4addr_t addr );
1.36 +int32_t mmu_ocache_data_read( sh4addr_t addr );
1.37 +int32_t mmu_utlb_addr_read( sh4addr_t addr );
1.38 +int32_t mmu_utlb_data_read( sh4addr_t addr );
1.39 +void mmu_icache_addr_write( sh4addr_t addr, uint32_t val );
1.40 +void mmu_icache_data_write( sh4addr_t addr, uint32_t val );
1.41 +void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val );
1.42 +void mmu_itlb_data_write( sh4addr_t addr, uint32_t val );
1.43 +void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val );
1.44 +void mmu_ocache_data_write( sh4addr_t addr, uint32_t val );
1.45 +void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val );
1.46 +void mmu_utlb_data_write( sh4addr_t addr, uint32_t val );
1.47 #endif
.