1.1 --- a/src/sh4/mmu.c	Wed Jul 16 10:40:10 2008 +0000
     1.2 +++ b/src/sh4/mmu.c	Wed Jul 30 22:50:44 2008 +0000
     1.3 @@ -58,8 +58,8 @@
     1.4      MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)));
     1.5  
     1.6  
     1.7 -#define OCRAM_START (0x1C000000>>PAGE_BITS)
     1.8 -#define OCRAM_END   (0x20000000>>PAGE_BITS)
     1.9 +#define OCRAM_START (0x1C000000>>LXDREAM_PAGE_BITS)
    1.10 +#define OCRAM_END   (0x20000000>>LXDREAM_PAGE_BITS)
    1.11  
    1.12  #define ITLB_ENTRY_COUNT 4
    1.13  #define UTLB_ENTRY_COUNT 64
    1.14 @@ -236,11 +236,11 @@
    1.15      switch( mode ) {
    1.16      case MEM_OC_INDEX0: /* OIX=0 */
    1.17          for( i=OCRAM_START; i<OCRAM_END; i++ )
    1.18 -            page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
    1.19 +            page_map[i] = cache + ((i&0x02)<<(LXDREAM_PAGE_BITS-1));
    1.20          break;
    1.21      case MEM_OC_INDEX1: /* OIX=1 */
    1.22          for( i=OCRAM_START; i<OCRAM_END; i++ )
    1.23 -            page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
    1.24 +            page_map[i] = cache + ((i&0x02000000)>>(25-LXDREAM_PAGE_BITS));
    1.25          break;
    1.26      default: /* disabled */
    1.27          for( i=OCRAM_START; i<OCRAM_END; i++ )