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lxdream.org :: lxdream/src/sh4/sh4x86.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 671:a530ea88eebd
prev669:ab344e42bca9
next673:44c579439d73
author nkeynes
date Thu May 15 10:22:39 2008 +0000 (13 years ago)
permissions -rw-r--r--
last change Permanently add SH4 instruction statistics tracking (enabled with --enable-sh4stats)
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.c Mon May 12 10:00:13 2008 +0000
1.2 +++ b/src/sh4/sh4x86.c Thu May 15 10:22:39 2008 +0000
1.3 @@ -28,6 +28,7 @@
1.4 #include "sh4/xltcache.h"
1.5 #include "sh4/sh4core.h"
1.6 #include "sh4/sh4trans.h"
1.7 +#include "sh4/sh4stat.h"
1.8 #include "sh4/sh4mmio.h"
1.9 #include "sh4/x86op.h"
1.10 #include "clock.h"
1.11 @@ -79,6 +80,12 @@
1.12 #define TSTATE_A 7
1.13 #define TSTATE_AE 3
1.14
1.15 +#ifdef ENABLE_SH4STATS
1.16 +#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
1.17 +#else
1.18 +#define COUNT_INST(id)
1.19 +#endif
1.20 +
1.21 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
1.22 #define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
1.23 CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
1.24 @@ -391,6 +398,7 @@
1.25 case 0x0:
1.26 { /* STC SR, Rn */
1.27 uint32_t Rn = ((ir>>8)&0xF);
1.28 + COUNT_INST(I_STCSR);
1.29 check_priv();
1.30 call_func0(sh4_read_sr);
1.31 store_reg( R_EAX, Rn );
1.32 @@ -400,6 +408,7 @@
1.33 case 0x1:
1.34 { /* STC GBR, Rn */
1.35 uint32_t Rn = ((ir>>8)&0xF);
1.36 + COUNT_INST(I_STC);
1.37 load_spreg( R_EAX, R_GBR );
1.38 store_reg( R_EAX, Rn );
1.39 }
1.40 @@ -407,6 +416,7 @@
1.41 case 0x2:
1.42 { /* STC VBR, Rn */
1.43 uint32_t Rn = ((ir>>8)&0xF);
1.44 + COUNT_INST(I_STC);
1.45 check_priv();
1.46 load_spreg( R_EAX, R_VBR );
1.47 store_reg( R_EAX, Rn );
1.48 @@ -416,6 +426,7 @@
1.49 case 0x3:
1.50 { /* STC SSR, Rn */
1.51 uint32_t Rn = ((ir>>8)&0xF);
1.52 + COUNT_INST(I_STC);
1.53 check_priv();
1.54 load_spreg( R_EAX, R_SSR );
1.55 store_reg( R_EAX, Rn );
1.56 @@ -425,6 +436,7 @@
1.57 case 0x4:
1.58 { /* STC SPC, Rn */
1.59 uint32_t Rn = ((ir>>8)&0xF);
1.60 + COUNT_INST(I_STC);
1.61 check_priv();
1.62 load_spreg( R_EAX, R_SPC );
1.63 store_reg( R_EAX, Rn );
1.64 @@ -439,6 +451,7 @@
1.65 case 0x1:
1.66 { /* STC Rm_BANK, Rn */
1.67 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
1.68 + COUNT_INST(I_STC);
1.69 check_priv();
1.70 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
1.71 store_reg( R_EAX, Rn );
1.72 @@ -452,6 +465,7 @@
1.73 case 0x0:
1.74 { /* BSRF Rn */
1.75 uint32_t Rn = ((ir>>8)&0xF);
1.76 + COUNT_INST(I_BSRF);
1.77 if( sh4_x86.in_delay_slot ) {
1.78 SLOTILLEGAL();
1.79 } else {
1.80 @@ -478,6 +492,7 @@
1.81 case 0x2:
1.82 { /* BRAF Rn */
1.83 uint32_t Rn = ((ir>>8)&0xF);
1.84 + COUNT_INST(I_BRAF);
1.85 if( sh4_x86.in_delay_slot ) {
1.86 SLOTILLEGAL();
1.87 } else {
1.88 @@ -502,6 +517,7 @@
1.89 case 0x8:
1.90 { /* PREF @Rn */
1.91 uint32_t Rn = ((ir>>8)&0xF);
1.92 + COUNT_INST(I_PREF);
1.93 load_reg( R_EAX, Rn );
1.94 MOV_r32_r32( R_EAX, R_ECX );
1.95 AND_imm32_r32( 0xFC000000, R_EAX );
1.96 @@ -517,21 +533,25 @@
1.97 case 0x9:
1.98 { /* OCBI @Rn */
1.99 uint32_t Rn = ((ir>>8)&0xF);
1.100 + COUNT_INST(I_OCBI);
1.101 }
1.102 break;
1.103 case 0xA:
1.104 { /* OCBP @Rn */
1.105 uint32_t Rn = ((ir>>8)&0xF);
1.106 + COUNT_INST(I_OCBP);
1.107 }
1.108 break;
1.109 case 0xB:
1.110 { /* OCBWB @Rn */
1.111 uint32_t Rn = ((ir>>8)&0xF);
1.112 + COUNT_INST(I_OCBWB);
1.113 }
1.114 break;
1.115 case 0xC:
1.116 { /* MOVCA.L R0, @Rn */
1.117 uint32_t Rn = ((ir>>8)&0xF);
1.118 + COUNT_INST(I_MOVCA);
1.119 load_reg( R_EAX, Rn );
1.120 check_walign32( R_EAX );
1.121 MMU_TRANSLATE_WRITE( R_EAX );
1.122 @@ -548,6 +568,7 @@
1.123 case 0x4:
1.124 { /* MOV.B Rm, @(R0, Rn) */
1.125 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.126 + COUNT_INST(I_MOVB);
1.127 load_reg( R_EAX, 0 );
1.128 load_reg( R_ECX, Rn );
1.129 ADD_r32_r32( R_ECX, R_EAX );
1.130 @@ -560,6 +581,7 @@
1.131 case 0x5:
1.132 { /* MOV.W Rm, @(R0, Rn) */
1.133 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.134 + COUNT_INST(I_MOVW);
1.135 load_reg( R_EAX, 0 );
1.136 load_reg( R_ECX, Rn );
1.137 ADD_r32_r32( R_ECX, R_EAX );
1.138 @@ -573,6 +595,7 @@
1.139 case 0x6:
1.140 { /* MOV.L Rm, @(R0, Rn) */
1.141 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.142 + COUNT_INST(I_MOVL);
1.143 load_reg( R_EAX, 0 );
1.144 load_reg( R_ECX, Rn );
1.145 ADD_r32_r32( R_ECX, R_EAX );
1.146 @@ -586,6 +609,7 @@
1.147 case 0x7:
1.148 { /* MUL.L Rm, Rn */
1.149 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.150 + COUNT_INST(I_MULL);
1.151 load_reg( R_EAX, Rm );
1.152 load_reg( R_ECX, Rn );
1.153 MUL_r32( R_ECX );
1.154 @@ -597,6 +621,7 @@
1.155 switch( (ir&0xFF0) >> 4 ) {
1.156 case 0x0:
1.157 { /* CLRT */
1.158 + COUNT_INST(I_CLRT);
1.159 CLC();
1.160 SETC_t();
1.161 sh4_x86.tstate = TSTATE_C;
1.162 @@ -604,6 +629,7 @@
1.163 break;
1.164 case 0x1:
1.165 { /* SETT */
1.166 + COUNT_INST(I_SETT);
1.167 STC();
1.168 SETC_t();
1.169 sh4_x86.tstate = TSTATE_C;
1.170 @@ -611,6 +637,7 @@
1.171 break;
1.172 case 0x2:
1.173 { /* CLRMAC */
1.174 + COUNT_INST(I_CLRMAC);
1.175 XOR_r32_r32(R_EAX, R_EAX);
1.176 store_spreg( R_EAX, R_MACL );
1.177 store_spreg( R_EAX, R_MACH );
1.178 @@ -619,11 +646,13 @@
1.179 break;
1.180 case 0x3:
1.181 { /* LDTLB */
1.182 + COUNT_INST(I_LDTLB);
1.183 call_func0( MMU_ldtlb );
1.184 }
1.185 break;
1.186 case 0x4:
1.187 { /* CLRS */
1.188 + COUNT_INST(I_CLRS);
1.189 CLC();
1.190 SETC_sh4r(R_S);
1.191 sh4_x86.tstate = TSTATE_C;
1.192 @@ -631,6 +660,7 @@
1.193 break;
1.194 case 0x5:
1.195 { /* SETS */
1.196 + COUNT_INST(I_SETS);
1.197 STC();
1.198 SETC_sh4r(R_S);
1.199 sh4_x86.tstate = TSTATE_C;
1.200 @@ -645,11 +675,13 @@
1.201 switch( (ir&0xF0) >> 4 ) {
1.202 case 0x0:
1.203 { /* NOP */
1.204 + COUNT_INST(I_NOP);
1.205 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
1.206 }
1.207 break;
1.208 case 0x1:
1.209 { /* DIV0U */
1.210 + COUNT_INST(I_DIV0U);
1.211 XOR_r32_r32( R_EAX, R_EAX );
1.212 store_spreg( R_EAX, R_Q );
1.213 store_spreg( R_EAX, R_M );
1.214 @@ -660,6 +692,7 @@
1.215 case 0x2:
1.216 { /* MOVT Rn */
1.217 uint32_t Rn = ((ir>>8)&0xF);
1.218 + COUNT_INST(I_MOVT);
1.219 load_spreg( R_EAX, R_T );
1.220 store_reg( R_EAX, Rn );
1.221 }
1.222 @@ -674,6 +707,7 @@
1.223 case 0x0:
1.224 { /* STS MACH, Rn */
1.225 uint32_t Rn = ((ir>>8)&0xF);
1.226 + COUNT_INST(I_STS);
1.227 load_spreg( R_EAX, R_MACH );
1.228 store_reg( R_EAX, Rn );
1.229 }
1.230 @@ -681,6 +715,7 @@
1.231 case 0x1:
1.232 { /* STS MACL, Rn */
1.233 uint32_t Rn = ((ir>>8)&0xF);
1.234 + COUNT_INST(I_STS);
1.235 load_spreg( R_EAX, R_MACL );
1.236 store_reg( R_EAX, Rn );
1.237 }
1.238 @@ -688,6 +723,7 @@
1.239 case 0x2:
1.240 { /* STS PR, Rn */
1.241 uint32_t Rn = ((ir>>8)&0xF);
1.242 + COUNT_INST(I_STS);
1.243 load_spreg( R_EAX, R_PR );
1.244 store_reg( R_EAX, Rn );
1.245 }
1.246 @@ -695,6 +731,7 @@
1.247 case 0x3:
1.248 { /* STC SGR, Rn */
1.249 uint32_t Rn = ((ir>>8)&0xF);
1.250 + COUNT_INST(I_STC);
1.251 check_priv();
1.252 load_spreg( R_EAX, R_SGR );
1.253 store_reg( R_EAX, Rn );
1.254 @@ -704,6 +741,7 @@
1.255 case 0x5:
1.256 { /* STS FPUL, Rn */
1.257 uint32_t Rn = ((ir>>8)&0xF);
1.258 + COUNT_INST(I_STS);
1.259 check_fpuen();
1.260 load_spreg( R_EAX, R_FPUL );
1.261 store_reg( R_EAX, Rn );
1.262 @@ -712,6 +750,7 @@
1.263 case 0x6:
1.264 { /* STS FPSCR, Rn */
1.265 uint32_t Rn = ((ir>>8)&0xF);
1.266 + COUNT_INST(I_STS);
1.267 check_fpuen();
1.268 load_spreg( R_EAX, R_FPSCR );
1.269 store_reg( R_EAX, Rn );
1.270 @@ -720,6 +759,7 @@
1.271 case 0xF:
1.272 { /* STC DBR, Rn */
1.273 uint32_t Rn = ((ir>>8)&0xF);
1.274 + COUNT_INST(I_STC);
1.275 check_priv();
1.276 load_spreg( R_EAX, R_DBR );
1.277 store_reg( R_EAX, Rn );
1.278 @@ -735,6 +775,7 @@
1.279 switch( (ir&0xFF0) >> 4 ) {
1.280 case 0x0:
1.281 { /* RTS */
1.282 + COUNT_INST(I_RTS);
1.283 if( sh4_x86.in_delay_slot ) {
1.284 SLOTILLEGAL();
1.285 } else {
1.286 @@ -755,6 +796,7 @@
1.287 break;
1.288 case 0x1:
1.289 { /* SLEEP */
1.290 + COUNT_INST(I_SLEEP);
1.291 check_priv();
1.292 call_func0( sh4_sleep );
1.293 sh4_x86.tstate = TSTATE_NONE;
1.294 @@ -764,6 +806,7 @@
1.295 break;
1.296 case 0x2:
1.297 { /* RTE */
1.298 + COUNT_INST(I_RTE);
1.299 if( sh4_x86.in_delay_slot ) {
1.300 SLOTILLEGAL();
1.301 } else {
1.302 @@ -796,6 +839,7 @@
1.303 case 0xC:
1.304 { /* MOV.B @(R0, Rm), Rn */
1.305 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.306 + COUNT_INST(I_MOVB);
1.307 load_reg( R_EAX, 0 );
1.308 load_reg( R_ECX, Rm );
1.309 ADD_r32_r32( R_ECX, R_EAX );
1.310 @@ -808,6 +852,7 @@
1.311 case 0xD:
1.312 { /* MOV.W @(R0, Rm), Rn */
1.313 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.314 + COUNT_INST(I_MOVW);
1.315 load_reg( R_EAX, 0 );
1.316 load_reg( R_ECX, Rm );
1.317 ADD_r32_r32( R_ECX, R_EAX );
1.318 @@ -821,6 +866,7 @@
1.319 case 0xE:
1.320 { /* MOV.L @(R0, Rm), Rn */
1.321 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.322 + COUNT_INST(I_MOVL);
1.323 load_reg( R_EAX, 0 );
1.324 load_reg( R_ECX, Rm );
1.325 ADD_r32_r32( R_ECX, R_EAX );
1.326 @@ -834,6 +880,7 @@
1.327 case 0xF:
1.328 { /* MAC.L @Rm+, @Rn+ */
1.329 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.330 + COUNT_INST(I_MACL);
1.331 if( Rm == Rn ) {
1.332 load_reg( R_EAX, Rm );
1.333 check_ralign32( R_EAX );
1.334 @@ -883,6 +930,7 @@
1.335 case 0x1:
1.336 { /* MOV.L Rm, @(disp, Rn) */
1.337 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1.338 + COUNT_INST(I_MOVL);
1.339 load_reg( R_EAX, Rn );
1.340 ADD_imm32_r32( disp, R_EAX );
1.341 check_walign32( R_EAX );
1.342 @@ -897,6 +945,7 @@
1.343 case 0x0:
1.344 { /* MOV.B Rm, @Rn */
1.345 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.346 + COUNT_INST(I_MOVB);
1.347 load_reg( R_EAX, Rn );
1.348 MMU_TRANSLATE_WRITE( R_EAX );
1.349 load_reg( R_EDX, Rm );
1.350 @@ -907,6 +956,7 @@
1.351 case 0x1:
1.352 { /* MOV.W Rm, @Rn */
1.353 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.354 + COUNT_INST(I_MOVW);
1.355 load_reg( R_EAX, Rn );
1.356 check_walign16( R_EAX );
1.357 MMU_TRANSLATE_WRITE( R_EAX )
1.358 @@ -918,6 +968,7 @@
1.359 case 0x2:
1.360 { /* MOV.L Rm, @Rn */
1.361 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.362 + COUNT_INST(I_MOVL);
1.363 load_reg( R_EAX, Rn );
1.364 check_walign32(R_EAX);
1.365 MMU_TRANSLATE_WRITE( R_EAX );
1.366 @@ -929,6 +980,7 @@
1.367 case 0x4:
1.368 { /* MOV.B Rm, @-Rn */
1.369 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.370 + COUNT_INST(I_MOVB);
1.371 load_reg( R_EAX, Rn );
1.372 ADD_imm8s_r32( -1, R_EAX );
1.373 MMU_TRANSLATE_WRITE( R_EAX );
1.374 @@ -941,6 +993,7 @@
1.375 case 0x5:
1.376 { /* MOV.W Rm, @-Rn */
1.377 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.378 + COUNT_INST(I_MOVW);
1.379 load_reg( R_EAX, Rn );
1.380 ADD_imm8s_r32( -2, R_EAX );
1.381 check_walign16( R_EAX );
1.382 @@ -954,6 +1007,7 @@
1.383 case 0x6:
1.384 { /* MOV.L Rm, @-Rn */
1.385 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.386 + COUNT_INST(I_MOVL);
1.387 load_reg( R_EAX, Rn );
1.388 ADD_imm8s_r32( -4, R_EAX );
1.389 check_walign32( R_EAX );
1.390 @@ -967,6 +1021,7 @@
1.391 case 0x7:
1.392 { /* DIV0S Rm, Rn */
1.393 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.394 + COUNT_INST(I_DIV0S);
1.395 load_reg( R_EAX, Rm );
1.396 load_reg( R_ECX, Rn );
1.397 SHR_imm8_r32( 31, R_EAX );
1.398 @@ -981,6 +1036,7 @@
1.399 case 0x8:
1.400 { /* TST Rm, Rn */
1.401 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.402 + COUNT_INST(I_TST);
1.403 load_reg( R_EAX, Rm );
1.404 load_reg( R_ECX, Rn );
1.405 TEST_r32_r32( R_EAX, R_ECX );
1.406 @@ -991,6 +1047,7 @@
1.407 case 0x9:
1.408 { /* AND Rm, Rn */
1.409 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.410 + COUNT_INST(I_AND);
1.411 load_reg( R_EAX, Rm );
1.412 load_reg( R_ECX, Rn );
1.413 AND_r32_r32( R_EAX, R_ECX );
1.414 @@ -1001,6 +1058,7 @@
1.415 case 0xA:
1.416 { /* XOR Rm, Rn */
1.417 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.418 + COUNT_INST(I_XOR);
1.419 load_reg( R_EAX, Rm );
1.420 load_reg( R_ECX, Rn );
1.421 XOR_r32_r32( R_EAX, R_ECX );
1.422 @@ -1011,6 +1069,7 @@
1.423 case 0xB:
1.424 { /* OR Rm, Rn */
1.425 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.426 + COUNT_INST(I_OR);
1.427 load_reg( R_EAX, Rm );
1.428 load_reg( R_ECX, Rn );
1.429 OR_r32_r32( R_EAX, R_ECX );
1.430 @@ -1021,6 +1080,7 @@
1.431 case 0xC:
1.432 { /* CMP/STR Rm, Rn */
1.433 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.434 + COUNT_INST(I_CMPSTR);
1.435 load_reg( R_EAX, Rm );
1.436 load_reg( R_ECX, Rn );
1.437 XOR_r32_r32( R_ECX, R_EAX );
1.438 @@ -1042,6 +1102,7 @@
1.439 case 0xD:
1.440 { /* XTRCT Rm, Rn */
1.441 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.442 + COUNT_INST(I_XTRCT);
1.443 load_reg( R_EAX, Rm );
1.444 load_reg( R_ECX, Rn );
1.445 SHL_imm8_r32( 16, R_EAX );
1.446 @@ -1054,6 +1115,7 @@
1.447 case 0xE:
1.448 { /* MULU.W Rm, Rn */
1.449 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.450 + COUNT_INST(I_MULUW);
1.451 load_reg16u( R_EAX, Rm );
1.452 load_reg16u( R_ECX, Rn );
1.453 MUL_r32( R_ECX );
1.454 @@ -1064,6 +1126,7 @@
1.455 case 0xF:
1.456 { /* MULS.W Rm, Rn */
1.457 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.458 + COUNT_INST(I_MULSW);
1.459 load_reg16s( R_EAX, Rm );
1.460 load_reg16s( R_ECX, Rn );
1.461 MUL_r32( R_ECX );
1.462 @@ -1081,6 +1144,7 @@
1.463 case 0x0:
1.464 { /* CMP/EQ Rm, Rn */
1.465 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.466 + COUNT_INST(I_CMPEQ);
1.467 load_reg( R_EAX, Rm );
1.468 load_reg( R_ECX, Rn );
1.469 CMP_r32_r32( R_EAX, R_ECX );
1.470 @@ -1091,6 +1155,7 @@
1.471 case 0x2:
1.472 { /* CMP/HS Rm, Rn */
1.473 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.474 + COUNT_INST(I_CMPHS);
1.475 load_reg( R_EAX, Rm );
1.476 load_reg( R_ECX, Rn );
1.477 CMP_r32_r32( R_EAX, R_ECX );
1.478 @@ -1101,6 +1166,7 @@
1.479 case 0x3:
1.480 { /* CMP/GE Rm, Rn */
1.481 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.482 + COUNT_INST(I_CMPGE);
1.483 load_reg( R_EAX, Rm );
1.484 load_reg( R_ECX, Rn );
1.485 CMP_r32_r32( R_EAX, R_ECX );
1.486 @@ -1111,6 +1177,7 @@
1.487 case 0x4:
1.488 { /* DIV1 Rm, Rn */
1.489 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.490 + COUNT_INST(I_DIV1);
1.491 load_spreg( R_ECX, R_M );
1.492 load_reg( R_EAX, Rn );
1.493 if( sh4_x86.tstate != TSTATE_C ) {
1.494 @@ -1139,6 +1206,7 @@
1.495 case 0x5:
1.496 { /* DMULU.L Rm, Rn */
1.497 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.498 + COUNT_INST(I_DMULU);
1.499 load_reg( R_EAX, Rm );
1.500 load_reg( R_ECX, Rn );
1.501 MUL_r32(R_ECX);
1.502 @@ -1150,6 +1218,7 @@
1.503 case 0x6:
1.504 { /* CMP/HI Rm, Rn */
1.505 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.506 + COUNT_INST(I_CMPHI);
1.507 load_reg( R_EAX, Rm );
1.508 load_reg( R_ECX, Rn );
1.509 CMP_r32_r32( R_EAX, R_ECX );
1.510 @@ -1160,6 +1229,7 @@
1.511 case 0x7:
1.512 { /* CMP/GT Rm, Rn */
1.513 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.514 + COUNT_INST(I_CMPGT);
1.515 load_reg( R_EAX, Rm );
1.516 load_reg( R_ECX, Rn );
1.517 CMP_r32_r32( R_EAX, R_ECX );
1.518 @@ -1170,6 +1240,7 @@
1.519 case 0x8:
1.520 { /* SUB Rm, Rn */
1.521 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.522 + COUNT_INST(I_SUB);
1.523 load_reg( R_EAX, Rm );
1.524 load_reg( R_ECX, Rn );
1.525 SUB_r32_r32( R_EAX, R_ECX );
1.526 @@ -1180,6 +1251,7 @@
1.527 case 0xA:
1.528 { /* SUBC Rm, Rn */
1.529 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.530 + COUNT_INST(I_SUBC);
1.531 load_reg( R_EAX, Rm );
1.532 load_reg( R_ECX, Rn );
1.533 if( sh4_x86.tstate != TSTATE_C ) {
1.534 @@ -1194,6 +1266,7 @@
1.535 case 0xB:
1.536 { /* SUBV Rm, Rn */
1.537 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.538 + COUNT_INST(I_SUBV);
1.539 load_reg( R_EAX, Rm );
1.540 load_reg( R_ECX, Rn );
1.541 SUB_r32_r32( R_EAX, R_ECX );
1.542 @@ -1205,6 +1278,7 @@
1.543 case 0xC:
1.544 { /* ADD Rm, Rn */
1.545 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.546 + COUNT_INST(I_ADD);
1.547 load_reg( R_EAX, Rm );
1.548 load_reg( R_ECX, Rn );
1.549 ADD_r32_r32( R_EAX, R_ECX );
1.550 @@ -1215,6 +1289,7 @@
1.551 case 0xD:
1.552 { /* DMULS.L Rm, Rn */
1.553 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.554 + COUNT_INST(I_DMULS);
1.555 load_reg( R_EAX, Rm );
1.556 load_reg( R_ECX, Rn );
1.557 IMUL_r32(R_ECX);
1.558 @@ -1226,6 +1301,7 @@
1.559 case 0xE:
1.560 { /* ADDC Rm, Rn */
1.561 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.562 + COUNT_INST(I_ADDC);
1.563 if( sh4_x86.tstate != TSTATE_C ) {
1.564 LDC_t();
1.565 }
1.566 @@ -1240,6 +1316,7 @@
1.567 case 0xF:
1.568 { /* ADDV Rm, Rn */
1.569 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.570 + COUNT_INST(I_ADDV);
1.571 load_reg( R_EAX, Rm );
1.572 load_reg( R_ECX, Rn );
1.573 ADD_r32_r32( R_EAX, R_ECX );
1.574 @@ -1260,6 +1337,7 @@
1.575 case 0x0:
1.576 { /* SHLL Rn */
1.577 uint32_t Rn = ((ir>>8)&0xF);
1.578 + COUNT_INST(I_SHLL);
1.579 load_reg( R_EAX, Rn );
1.580 SHL1_r32( R_EAX );
1.581 SETC_t();
1.582 @@ -1270,6 +1348,7 @@
1.583 case 0x1:
1.584 { /* DT Rn */
1.585 uint32_t Rn = ((ir>>8)&0xF);
1.586 + COUNT_INST(I_DT);
1.587 load_reg( R_EAX, Rn );
1.588 ADD_imm8s_r32( -1, R_EAX );
1.589 store_reg( R_EAX, Rn );
1.590 @@ -1280,6 +1359,7 @@
1.591 case 0x2:
1.592 { /* SHAL Rn */
1.593 uint32_t Rn = ((ir>>8)&0xF);
1.594 + COUNT_INST(I_SHAL);
1.595 load_reg( R_EAX, Rn );
1.596 SHL1_r32( R_EAX );
1.597 SETC_t();
1.598 @@ -1297,6 +1377,7 @@
1.599 case 0x0:
1.600 { /* SHLR Rn */
1.601 uint32_t Rn = ((ir>>8)&0xF);
1.602 + COUNT_INST(I_SHLR);
1.603 load_reg( R_EAX, Rn );
1.604 SHR1_r32( R_EAX );
1.605 SETC_t();
1.606 @@ -1307,6 +1388,7 @@
1.607 case 0x1:
1.608 { /* CMP/PZ Rn */
1.609 uint32_t Rn = ((ir>>8)&0xF);
1.610 + COUNT_INST(I_CMPPZ);
1.611 load_reg( R_EAX, Rn );
1.612 CMP_imm8s_r32( 0, R_EAX );
1.613 SETGE_t();
1.614 @@ -1316,6 +1398,7 @@
1.615 case 0x2:
1.616 { /* SHAR Rn */
1.617 uint32_t Rn = ((ir>>8)&0xF);
1.618 + COUNT_INST(I_SHAR);
1.619 load_reg( R_EAX, Rn );
1.620 SAR1_r32( R_EAX );
1.621 SETC_t();
1.622 @@ -1333,6 +1416,7 @@
1.623 case 0x0:
1.624 { /* STS.L MACH, @-Rn */
1.625 uint32_t Rn = ((ir>>8)&0xF);
1.626 + COUNT_INST(I_STSM);
1.627 load_reg( R_EAX, Rn );
1.628 check_walign32( R_EAX );
1.629 ADD_imm8s_r32( -4, R_EAX );
1.630 @@ -1346,6 +1430,7 @@
1.631 case 0x1:
1.632 { /* STS.L MACL, @-Rn */
1.633 uint32_t Rn = ((ir>>8)&0xF);
1.634 + COUNT_INST(I_STSM);
1.635 load_reg( R_EAX, Rn );
1.636 check_walign32( R_EAX );
1.637 ADD_imm8s_r32( -4, R_EAX );
1.638 @@ -1359,6 +1444,7 @@
1.639 case 0x2:
1.640 { /* STS.L PR, @-Rn */
1.641 uint32_t Rn = ((ir>>8)&0xF);
1.642 + COUNT_INST(I_STSM);
1.643 load_reg( R_EAX, Rn );
1.644 check_walign32( R_EAX );
1.645 ADD_imm8s_r32( -4, R_EAX );
1.646 @@ -1372,6 +1458,7 @@
1.647 case 0x3:
1.648 { /* STC.L SGR, @-Rn */
1.649 uint32_t Rn = ((ir>>8)&0xF);
1.650 + COUNT_INST(I_STCM);
1.651 check_priv();
1.652 load_reg( R_EAX, Rn );
1.653 check_walign32( R_EAX );
1.654 @@ -1386,6 +1473,7 @@
1.655 case 0x5:
1.656 { /* STS.L FPUL, @-Rn */
1.657 uint32_t Rn = ((ir>>8)&0xF);
1.658 + COUNT_INST(I_STSM);
1.659 check_fpuen();
1.660 load_reg( R_EAX, Rn );
1.661 check_walign32( R_EAX );
1.662 @@ -1400,6 +1488,7 @@
1.663 case 0x6:
1.664 { /* STS.L FPSCR, @-Rn */
1.665 uint32_t Rn = ((ir>>8)&0xF);
1.666 + COUNT_INST(I_STSM);
1.667 check_fpuen();
1.668 load_reg( R_EAX, Rn );
1.669 check_walign32( R_EAX );
1.670 @@ -1414,6 +1503,7 @@
1.671 case 0xF:
1.672 { /* STC.L DBR, @-Rn */
1.673 uint32_t Rn = ((ir>>8)&0xF);
1.674 + COUNT_INST(I_STCM);
1.675 check_priv();
1.676 load_reg( R_EAX, Rn );
1.677 check_walign32( R_EAX );
1.678 @@ -1437,6 +1527,7 @@
1.679 case 0x0:
1.680 { /* STC.L SR, @-Rn */
1.681 uint32_t Rn = ((ir>>8)&0xF);
1.682 + COUNT_INST(I_STCSRM);
1.683 check_priv();
1.684 load_reg( R_EAX, Rn );
1.685 check_walign32( R_EAX );
1.686 @@ -1453,6 +1544,7 @@
1.687 case 0x1:
1.688 { /* STC.L GBR, @-Rn */
1.689 uint32_t Rn = ((ir>>8)&0xF);
1.690 + COUNT_INST(I_STCM);
1.691 load_reg( R_EAX, Rn );
1.692 check_walign32( R_EAX );
1.693 ADD_imm8s_r32( -4, R_EAX );
1.694 @@ -1466,6 +1558,7 @@
1.695 case 0x2:
1.696 { /* STC.L VBR, @-Rn */
1.697 uint32_t Rn = ((ir>>8)&0xF);
1.698 + COUNT_INST(I_STCM);
1.699 check_priv();
1.700 load_reg( R_EAX, Rn );
1.701 check_walign32( R_EAX );
1.702 @@ -1480,6 +1573,7 @@
1.703 case 0x3:
1.704 { /* STC.L SSR, @-Rn */
1.705 uint32_t Rn = ((ir>>8)&0xF);
1.706 + COUNT_INST(I_STCM);
1.707 check_priv();
1.708 load_reg( R_EAX, Rn );
1.709 check_walign32( R_EAX );
1.710 @@ -1494,6 +1588,7 @@
1.711 case 0x4:
1.712 { /* STC.L SPC, @-Rn */
1.713 uint32_t Rn = ((ir>>8)&0xF);
1.714 + COUNT_INST(I_STCM);
1.715 check_priv();
1.716 load_reg( R_EAX, Rn );
1.717 check_walign32( R_EAX );
1.718 @@ -1513,6 +1608,7 @@
1.719 case 0x1:
1.720 { /* STC.L Rm_BANK, @-Rn */
1.721 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
1.722 + COUNT_INST(I_STCM);
1.723 check_priv();
1.724 load_reg( R_EAX, Rn );
1.725 check_walign32( R_EAX );
1.726 @@ -1531,6 +1627,7 @@
1.727 case 0x0:
1.728 { /* ROTL Rn */
1.729 uint32_t Rn = ((ir>>8)&0xF);
1.730 + COUNT_INST(I_ROTL);
1.731 load_reg( R_EAX, Rn );
1.732 ROL1_r32( R_EAX );
1.733 store_reg( R_EAX, Rn );
1.734 @@ -1541,6 +1638,7 @@
1.735 case 0x2:
1.736 { /* ROTCL Rn */
1.737 uint32_t Rn = ((ir>>8)&0xF);
1.738 + COUNT_INST(I_ROTCL);
1.739 load_reg( R_EAX, Rn );
1.740 if( sh4_x86.tstate != TSTATE_C ) {
1.741 LDC_t();
1.742 @@ -1561,6 +1659,7 @@
1.743 case 0x0:
1.744 { /* ROTR Rn */
1.745 uint32_t Rn = ((ir>>8)&0xF);
1.746 + COUNT_INST(I_ROTR);
1.747 load_reg( R_EAX, Rn );
1.748 ROR1_r32( R_EAX );
1.749 store_reg( R_EAX, Rn );
1.750 @@ -1571,6 +1670,7 @@
1.751 case 0x1:
1.752 { /* CMP/PL Rn */
1.753 uint32_t Rn = ((ir>>8)&0xF);
1.754 + COUNT_INST(I_CMPPL);
1.755 load_reg( R_EAX, Rn );
1.756 CMP_imm8s_r32( 0, R_EAX );
1.757 SETG_t();
1.758 @@ -1580,6 +1680,7 @@
1.759 case 0x2:
1.760 { /* ROTCR Rn */
1.761 uint32_t Rn = ((ir>>8)&0xF);
1.762 + COUNT_INST(I_ROTCR);
1.763 load_reg( R_EAX, Rn );
1.764 if( sh4_x86.tstate != TSTATE_C ) {
1.765 LDC_t();
1.766 @@ -1600,6 +1701,7 @@
1.767 case 0x0:
1.768 { /* LDS.L @Rm+, MACH */
1.769 uint32_t Rm = ((ir>>8)&0xF);
1.770 + COUNT_INST(I_LDSM);
1.771 load_reg( R_EAX, Rm );
1.772 check_ralign32( R_EAX );
1.773 MMU_TRANSLATE_READ( R_EAX );
1.774 @@ -1612,6 +1714,7 @@
1.775 case 0x1:
1.776 { /* LDS.L @Rm+, MACL */
1.777 uint32_t Rm = ((ir>>8)&0xF);
1.778 + COUNT_INST(I_LDSM);
1.779 load_reg( R_EAX, Rm );
1.780 check_ralign32( R_EAX );
1.781 MMU_TRANSLATE_READ( R_EAX );
1.782 @@ -1624,6 +1727,7 @@
1.783 case 0x2:
1.784 { /* LDS.L @Rm+, PR */
1.785 uint32_t Rm = ((ir>>8)&0xF);
1.786 + COUNT_INST(I_LDSM);
1.787 load_reg( R_EAX, Rm );
1.788 check_ralign32( R_EAX );
1.789 MMU_TRANSLATE_READ( R_EAX );
1.790 @@ -1636,6 +1740,7 @@
1.791 case 0x3:
1.792 { /* LDC.L @Rm+, SGR */
1.793 uint32_t Rm = ((ir>>8)&0xF);
1.794 + COUNT_INST(I_LDCM);
1.795 check_priv();
1.796 load_reg( R_EAX, Rm );
1.797 check_ralign32( R_EAX );
1.798 @@ -1649,6 +1754,7 @@
1.799 case 0x5:
1.800 { /* LDS.L @Rm+, FPUL */
1.801 uint32_t Rm = ((ir>>8)&0xF);
1.802 + COUNT_INST(I_LDSM);
1.803 check_fpuen();
1.804 load_reg( R_EAX, Rm );
1.805 check_ralign32( R_EAX );
1.806 @@ -1662,6 +1768,7 @@
1.807 case 0x6:
1.808 { /* LDS.L @Rm+, FPSCR */
1.809 uint32_t Rm = ((ir>>8)&0xF);
1.810 + COUNT_INST(I_LDS);
1.811 check_fpuen();
1.812 load_reg( R_EAX, Rm );
1.813 check_ralign32( R_EAX );
1.814 @@ -1675,6 +1782,7 @@
1.815 case 0xF:
1.816 { /* LDC.L @Rm+, DBR */
1.817 uint32_t Rm = ((ir>>8)&0xF);
1.818 + COUNT_INST(I_LDCM);
1.819 check_priv();
1.820 load_reg( R_EAX, Rm );
1.821 check_ralign32( R_EAX );
1.822 @@ -1697,6 +1805,7 @@
1.823 case 0x0:
1.824 { /* LDC.L @Rm+, SR */
1.825 uint32_t Rm = ((ir>>8)&0xF);
1.826 + COUNT_INST(I_LDCSRM);
1.827 if( sh4_x86.in_delay_slot ) {
1.828 SLOTILLEGAL();
1.829 } else {
1.830 @@ -1716,6 +1825,7 @@
1.831 case 0x1:
1.832 { /* LDC.L @Rm+, GBR */
1.833 uint32_t Rm = ((ir>>8)&0xF);
1.834 + COUNT_INST(I_LDCM);
1.835 load_reg( R_EAX, Rm );
1.836 check_ralign32( R_EAX );
1.837 MMU_TRANSLATE_READ( R_EAX );
1.838 @@ -1728,6 +1838,7 @@
1.839 case 0x2:
1.840 { /* LDC.L @Rm+, VBR */
1.841 uint32_t Rm = ((ir>>8)&0xF);
1.842 + COUNT_INST(I_LDCM);
1.843 check_priv();
1.844 load_reg( R_EAX, Rm );
1.845 check_ralign32( R_EAX );
1.846 @@ -1741,6 +1852,7 @@
1.847 case 0x3:
1.848 { /* LDC.L @Rm+, SSR */
1.849 uint32_t Rm = ((ir>>8)&0xF);
1.850 + COUNT_INST(I_LDCM);
1.851 check_priv();
1.852 load_reg( R_EAX, Rm );
1.853 check_ralign32( R_EAX );
1.854 @@ -1754,6 +1866,7 @@
1.855 case 0x4:
1.856 { /* LDC.L @Rm+, SPC */
1.857 uint32_t Rm = ((ir>>8)&0xF);
1.858 + COUNT_INST(I_LDCM);
1.859 check_priv();
1.860 load_reg( R_EAX, Rm );
1.861 check_ralign32( R_EAX );
1.862 @@ -1772,6 +1885,7 @@
1.863 case 0x1:
1.864 { /* LDC.L @Rm+, Rn_BANK */
1.865 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1.866 + COUNT_INST(I_LDCM);
1.867 check_priv();
1.868 load_reg( R_EAX, Rm );
1.869 check_ralign32( R_EAX );
1.870 @@ -1789,6 +1903,7 @@
1.871 case 0x0:
1.872 { /* SHLL2 Rn */
1.873 uint32_t Rn = ((ir>>8)&0xF);
1.874 + COUNT_INST(I_SHLL);
1.875 load_reg( R_EAX, Rn );
1.876 SHL_imm8_r32( 2, R_EAX );
1.877 store_reg( R_EAX, Rn );
1.878 @@ -1798,6 +1913,7 @@
1.879 case 0x1:
1.880 { /* SHLL8 Rn */
1.881 uint32_t Rn = ((ir>>8)&0xF);
1.882 + COUNT_INST(I_SHLL);
1.883 load_reg( R_EAX, Rn );
1.884 SHL_imm8_r32( 8, R_EAX );
1.885 store_reg( R_EAX, Rn );
1.886 @@ -1807,6 +1923,7 @@
1.887 case 0x2:
1.888 { /* SHLL16 Rn */
1.889 uint32_t Rn = ((ir>>8)&0xF);
1.890 + COUNT_INST(I_SHLL);
1.891 load_reg( R_EAX, Rn );
1.892 SHL_imm8_r32( 16, R_EAX );
1.893 store_reg( R_EAX, Rn );
1.894 @@ -1823,6 +1940,7 @@
1.895 case 0x0:
1.896 { /* SHLR2 Rn */
1.897 uint32_t Rn = ((ir>>8)&0xF);
1.898 + COUNT_INST(I_SHLR);
1.899 load_reg( R_EAX, Rn );
1.900 SHR_imm8_r32( 2, R_EAX );
1.901 store_reg( R_EAX, Rn );
1.902 @@ -1832,6 +1950,7 @@
1.903 case 0x1:
1.904 { /* SHLR8 Rn */
1.905 uint32_t Rn = ((ir>>8)&0xF);
1.906 + COUNT_INST(I_SHLR);
1.907 load_reg( R_EAX, Rn );
1.908 SHR_imm8_r32( 8, R_EAX );
1.909 store_reg( R_EAX, Rn );
1.910 @@ -1841,6 +1960,7 @@
1.911 case 0x2:
1.912 { /* SHLR16 Rn */
1.913 uint32_t Rn = ((ir>>8)&0xF);
1.914 + COUNT_INST(I_SHLR);
1.915 load_reg( R_EAX, Rn );
1.916 SHR_imm8_r32( 16, R_EAX );
1.917 store_reg( R_EAX, Rn );
1.918 @@ -1857,6 +1977,7 @@
1.919 case 0x0:
1.920 { /* LDS Rm, MACH */
1.921 uint32_t Rm = ((ir>>8)&0xF);
1.922 + COUNT_INST(I_LDS);
1.923 load_reg( R_EAX, Rm );
1.924 store_spreg( R_EAX, R_MACH );
1.925 }
1.926 @@ -1864,6 +1985,7 @@
1.927 case 0x1:
1.928 { /* LDS Rm, MACL */
1.929 uint32_t Rm = ((ir>>8)&0xF);
1.930 + COUNT_INST(I_LDS);
1.931 load_reg( R_EAX, Rm );
1.932 store_spreg( R_EAX, R_MACL );
1.933 }
1.934 @@ -1871,6 +1993,7 @@
1.935 case 0x2:
1.936 { /* LDS Rm, PR */
1.937 uint32_t Rm = ((ir>>8)&0xF);
1.938 + COUNT_INST(I_LDS);
1.939 load_reg( R_EAX, Rm );
1.940 store_spreg( R_EAX, R_PR );
1.941 }
1.942 @@ -1878,6 +2001,7 @@
1.943 case 0x3:
1.944 { /* LDC Rm, SGR */
1.945 uint32_t Rm = ((ir>>8)&0xF);
1.946 + COUNT_INST(I_LDC);
1.947 check_priv();
1.948 load_reg( R_EAX, Rm );
1.949 store_spreg( R_EAX, R_SGR );
1.950 @@ -1887,6 +2011,7 @@
1.951 case 0x5:
1.952 { /* LDS Rm, FPUL */
1.953 uint32_t Rm = ((ir>>8)&0xF);
1.954 + COUNT_INST(I_LDS);
1.955 check_fpuen();
1.956 load_reg( R_EAX, Rm );
1.957 store_spreg( R_EAX, R_FPUL );
1.958 @@ -1895,6 +2020,7 @@
1.959 case 0x6:
1.960 { /* LDS Rm, FPSCR */
1.961 uint32_t Rm = ((ir>>8)&0xF);
1.962 + COUNT_INST(I_LDS);
1.963 check_fpuen();
1.964 load_reg( R_EAX, Rm );
1.965 call_func1( sh4_write_fpscr, R_EAX );
1.966 @@ -1904,6 +2030,7 @@
1.967 case 0xF:
1.968 { /* LDC Rm, DBR */
1.969 uint32_t Rm = ((ir>>8)&0xF);
1.970 + COUNT_INST(I_LDC);
1.971 check_priv();
1.972 load_reg( R_EAX, Rm );
1.973 store_spreg( R_EAX, R_DBR );
1.974 @@ -1920,6 +2047,7 @@
1.975 case 0x0:
1.976 { /* JSR @Rn */
1.977 uint32_t Rn = ((ir>>8)&0xF);
1.978 + COUNT_INST(I_JSR);
1.979 if( sh4_x86.in_delay_slot ) {
1.980 SLOTILLEGAL();
1.981 } else {
1.982 @@ -1945,6 +2073,7 @@
1.983 case 0x1:
1.984 { /* TAS.B @Rn */
1.985 uint32_t Rn = ((ir>>8)&0xF);
1.986 + COUNT_INST(I_TASB);
1.987 load_reg( R_EAX, Rn );
1.988 MMU_TRANSLATE_WRITE( R_EAX );
1.989 PUSH_realigned_r32( R_EAX );
1.990 @@ -1960,6 +2089,7 @@
1.991 case 0x2:
1.992 { /* JMP @Rn */
1.993 uint32_t Rn = ((ir>>8)&0xF);
1.994 + COUNT_INST(I_JMP);
1.995 if( sh4_x86.in_delay_slot ) {
1.996 SLOTILLEGAL();
1.997 } else {
1.998 @@ -1986,6 +2116,7 @@
1.999 case 0xC:
1.1000 { /* SHAD Rm, Rn */
1.1001 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1002 + COUNT_INST(I_SHAD);
1.1003 /* Annoyingly enough, not directly convertible */
1.1004 load_reg( R_EAX, Rn );
1.1005 load_reg( R_ECX, Rm );
1.1006 @@ -2014,6 +2145,7 @@
1.1007 case 0xD:
1.1008 { /* SHLD Rm, Rn */
1.1009 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1010 + COUNT_INST(I_SHLD);
1.1011 load_reg( R_EAX, Rn );
1.1012 load_reg( R_ECX, Rm );
1.1013 CMP_imm32_r32( 0, R_ECX );
1.1014 @@ -2045,6 +2177,7 @@
1.1015 case 0x0:
1.1016 { /* LDC Rm, SR */
1.1017 uint32_t Rm = ((ir>>8)&0xF);
1.1018 + COUNT_INST(I_LDCSR);
1.1019 if( sh4_x86.in_delay_slot ) {
1.1020 SLOTILLEGAL();
1.1021 } else {
1.1022 @@ -2060,6 +2193,7 @@
1.1023 case 0x1:
1.1024 { /* LDC Rm, GBR */
1.1025 uint32_t Rm = ((ir>>8)&0xF);
1.1026 + COUNT_INST(I_LDC);
1.1027 load_reg( R_EAX, Rm );
1.1028 store_spreg( R_EAX, R_GBR );
1.1029 }
1.1030 @@ -2067,6 +2201,7 @@
1.1031 case 0x2:
1.1032 { /* LDC Rm, VBR */
1.1033 uint32_t Rm = ((ir>>8)&0xF);
1.1034 + COUNT_INST(I_LDC);
1.1035 check_priv();
1.1036 load_reg( R_EAX, Rm );
1.1037 store_spreg( R_EAX, R_VBR );
1.1038 @@ -2076,6 +2211,7 @@
1.1039 case 0x3:
1.1040 { /* LDC Rm, SSR */
1.1041 uint32_t Rm = ((ir>>8)&0xF);
1.1042 + COUNT_INST(I_LDC);
1.1043 check_priv();
1.1044 load_reg( R_EAX, Rm );
1.1045 store_spreg( R_EAX, R_SSR );
1.1046 @@ -2085,6 +2221,7 @@
1.1047 case 0x4:
1.1048 { /* LDC Rm, SPC */
1.1049 uint32_t Rm = ((ir>>8)&0xF);
1.1050 + COUNT_INST(I_LDC);
1.1051 check_priv();
1.1052 load_reg( R_EAX, Rm );
1.1053 store_spreg( R_EAX, R_SPC );
1.1054 @@ -2099,6 +2236,7 @@
1.1055 case 0x1:
1.1056 { /* LDC Rm, Rn_BANK */
1.1057 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1.1058 + COUNT_INST(I_LDC);
1.1059 check_priv();
1.1060 load_reg( R_EAX, Rm );
1.1061 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
1.1062 @@ -2110,6 +2248,7 @@
1.1063 case 0xF:
1.1064 { /* MAC.W @Rm+, @Rn+ */
1.1065 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1066 + COUNT_INST(I_MACW);
1.1067 if( Rm == Rn ) {
1.1068 load_reg( R_EAX, Rm );
1.1069 check_ralign16( R_EAX );
1.1070 @@ -2172,6 +2311,7 @@
1.1071 case 0x5:
1.1072 { /* MOV.L @(disp, Rm), Rn */
1.1073 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1.1074 + COUNT_INST(I_MOVL);
1.1075 load_reg( R_EAX, Rm );
1.1076 ADD_imm8s_r32( disp, R_EAX );
1.1077 check_ralign32( R_EAX );
1.1078 @@ -2186,6 +2326,7 @@
1.1079 case 0x0:
1.1080 { /* MOV.B @Rm, Rn */
1.1081 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1082 + COUNT_INST(I_MOVB);
1.1083 load_reg( R_EAX, Rm );
1.1084 MMU_TRANSLATE_READ( R_EAX );
1.1085 MEM_READ_BYTE( R_EAX, R_EAX );
1.1086 @@ -2196,6 +2337,7 @@
1.1087 case 0x1:
1.1088 { /* MOV.W @Rm, Rn */
1.1089 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1090 + COUNT_INST(I_MOVW);
1.1091 load_reg( R_EAX, Rm );
1.1092 check_ralign16( R_EAX );
1.1093 MMU_TRANSLATE_READ( R_EAX );
1.1094 @@ -2207,6 +2349,7 @@
1.1095 case 0x2:
1.1096 { /* MOV.L @Rm, Rn */
1.1097 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1098 + COUNT_INST(I_MOVL);
1.1099 load_reg( R_EAX, Rm );
1.1100 check_ralign32( R_EAX );
1.1101 MMU_TRANSLATE_READ( R_EAX );
1.1102 @@ -2218,6 +2361,7 @@
1.1103 case 0x3:
1.1104 { /* MOV Rm, Rn */
1.1105 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1106 + COUNT_INST(I_MOV);
1.1107 load_reg( R_EAX, Rm );
1.1108 store_reg( R_EAX, Rn );
1.1109 }
1.1110 @@ -2225,6 +2369,7 @@
1.1111 case 0x4:
1.1112 { /* MOV.B @Rm+, Rn */
1.1113 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1114 + COUNT_INST(I_MOVB);
1.1115 load_reg( R_EAX, Rm );
1.1116 MMU_TRANSLATE_READ( R_EAX );
1.1117 ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
1.1118 @@ -2236,6 +2381,7 @@
1.1119 case 0x5:
1.1120 { /* MOV.W @Rm+, Rn */
1.1121 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1122 + COUNT_INST(I_MOVW);
1.1123 load_reg( R_EAX, Rm );
1.1124 check_ralign16( R_EAX );
1.1125 MMU_TRANSLATE_READ( R_EAX );
1.1126 @@ -2248,6 +2394,7 @@
1.1127 case 0x6:
1.1128 { /* MOV.L @Rm+, Rn */
1.1129 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1130 + COUNT_INST(I_MOVL);
1.1131 load_reg( R_EAX, Rm );
1.1132 check_ralign32( R_EAX );
1.1133 MMU_TRANSLATE_READ( R_EAX );
1.1134 @@ -2260,6 +2407,7 @@
1.1135 case 0x7:
1.1136 { /* NOT Rm, Rn */
1.1137 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1138 + COUNT_INST(I_NOT);
1.1139 load_reg( R_EAX, Rm );
1.1140 NOT_r32( R_EAX );
1.1141 store_reg( R_EAX, Rn );
1.1142 @@ -2269,6 +2417,7 @@
1.1143 case 0x8:
1.1144 { /* SWAP.B Rm, Rn */
1.1145 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1146 + COUNT_INST(I_SWAPB);
1.1147 load_reg( R_EAX, Rm );
1.1148 XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
1.1149 store_reg( R_EAX, Rn );
1.1150 @@ -2277,6 +2426,7 @@
1.1151 case 0x9:
1.1152 { /* SWAP.W Rm, Rn */
1.1153 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1154 + COUNT_INST(I_SWAPB);
1.1155 load_reg( R_EAX, Rm );
1.1156 MOV_r32_r32( R_EAX, R_ECX );
1.1157 SHL_imm8_r32( 16, R_ECX );
1.1158 @@ -2289,6 +2439,7 @@
1.1159 case 0xA:
1.1160 { /* NEGC Rm, Rn */
1.1161 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1162 + COUNT_INST(I_NEGC);
1.1163 load_reg( R_EAX, Rm );
1.1164 XOR_r32_r32( R_ECX, R_ECX );
1.1165 LDC_t();
1.1166 @@ -2301,6 +2452,7 @@
1.1167 case 0xB:
1.1168 { /* NEG Rm, Rn */
1.1169 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1170 + COUNT_INST(I_NEG);
1.1171 load_reg( R_EAX, Rm );
1.1172 NEG_r32( R_EAX );
1.1173 store_reg( R_EAX, Rn );
1.1174 @@ -2310,6 +2462,7 @@
1.1175 case 0xC:
1.1176 { /* EXTU.B Rm, Rn */
1.1177 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1178 + COUNT_INST(I_EXTUB);
1.1179 load_reg( R_EAX, Rm );
1.1180 MOVZX_r8_r32( R_EAX, R_EAX );
1.1181 store_reg( R_EAX, Rn );
1.1182 @@ -2318,6 +2471,7 @@
1.1183 case 0xD:
1.1184 { /* EXTU.W Rm, Rn */
1.1185 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1186 + COUNT_INST(I_EXTUW);
1.1187 load_reg( R_EAX, Rm );
1.1188 MOVZX_r16_r32( R_EAX, R_EAX );
1.1189 store_reg( R_EAX, Rn );
1.1190 @@ -2326,6 +2480,7 @@
1.1191 case 0xE:
1.1192 { /* EXTS.B Rm, Rn */
1.1193 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1194 + COUNT_INST(I_EXTSB);
1.1195 load_reg( R_EAX, Rm );
1.1196 MOVSX_r8_r32( R_EAX, R_EAX );
1.1197 store_reg( R_EAX, Rn );
1.1198 @@ -2334,6 +2489,7 @@
1.1199 case 0xF:
1.1200 { /* EXTS.W Rm, Rn */
1.1201 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1202 + COUNT_INST(I_EXTSW);
1.1203 load_reg( R_EAX, Rm );
1.1204 MOVSX_r16_r32( R_EAX, R_EAX );
1.1205 store_reg( R_EAX, Rn );
1.1206 @@ -2344,6 +2500,7 @@
1.1207 case 0x7:
1.1208 { /* ADD #imm, Rn */
1.1209 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1.1210 + COUNT_INST(I_ADDI);
1.1211 load_reg( R_EAX, Rn );
1.1212 ADD_imm8s_r32( imm, R_EAX );
1.1213 store_reg( R_EAX, Rn );
1.1214 @@ -2355,6 +2512,7 @@
1.1215 case 0x0:
1.1216 { /* MOV.B R0, @(disp, Rn) */
1.1217 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1.1218 + COUNT_INST(I_MOVB);
1.1219 load_reg( R_EAX, Rn );
1.1220 ADD_imm32_r32( disp, R_EAX );
1.1221 MMU_TRANSLATE_WRITE( R_EAX );
1.1222 @@ -2366,6 +2524,7 @@
1.1223 case 0x1:
1.1224 { /* MOV.W R0, @(disp, Rn) */
1.1225 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1.1226 + COUNT_INST(I_MOVW);
1.1227 load_reg( R_EAX, Rn );
1.1228 ADD_imm32_r32( disp, R_EAX );
1.1229 check_walign16( R_EAX );
1.1230 @@ -2378,6 +2537,7 @@
1.1231 case 0x4:
1.1232 { /* MOV.B @(disp, Rm), R0 */
1.1233 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1.1234 + COUNT_INST(I_MOVB);
1.1235 load_reg( R_EAX, Rm );
1.1236 ADD_imm32_r32( disp, R_EAX );
1.1237 MMU_TRANSLATE_READ( R_EAX );
1.1238 @@ -2389,6 +2549,7 @@
1.1239 case 0x5:
1.1240 { /* MOV.W @(disp, Rm), R0 */
1.1241 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1.1242 + COUNT_INST(I_MOVW);
1.1243 load_reg( R_EAX, Rm );
1.1244 ADD_imm32_r32( disp, R_EAX );
1.1245 check_ralign16( R_EAX );
1.1246 @@ -2401,6 +2562,7 @@
1.1247 case 0x8:
1.1248 { /* CMP/EQ #imm, R0 */
1.1249 int32_t imm = SIGNEXT8(ir&0xFF);
1.1250 + COUNT_INST(I_CMPEQI);
1.1251 load_reg( R_EAX, 0 );
1.1252 CMP_imm8s_r32(imm, R_EAX);
1.1253 SETE_t();
1.1254 @@ -2410,6 +2572,7 @@
1.1255 case 0x9:
1.1256 { /* BT disp */
1.1257 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1.1258 + COUNT_INST(I_BT);
1.1259 if( sh4_x86.in_delay_slot ) {
1.1260 SLOTILLEGAL();
1.1261 } else {
1.1262 @@ -2424,6 +2587,7 @@
1.1263 case 0xB:
1.1264 { /* BF disp */
1.1265 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1.1266 + COUNT_INST(I_BF);
1.1267 if( sh4_x86.in_delay_slot ) {
1.1268 SLOTILLEGAL();
1.1269 } else {
1.1270 @@ -2438,6 +2602,7 @@
1.1271 case 0xD:
1.1272 { /* BT/S disp */
1.1273 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1.1274 + COUNT_INST(I_BTS);
1.1275 if( sh4_x86.in_delay_slot ) {
1.1276 SLOTILLEGAL();
1.1277 } else {
1.1278 @@ -2471,6 +2636,7 @@
1.1279 case 0xF:
1.1280 { /* BF/S disp */
1.1281 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1.1282 + COUNT_INST(I_BFS);
1.1283 if( sh4_x86.in_delay_slot ) {
1.1284 SLOTILLEGAL();
1.1285 } else {
1.1286 @@ -2511,6 +2677,7 @@
1.1287 case 0x9:
1.1288 { /* MOV.W @(disp, PC), Rn */
1.1289 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1.1290 + COUNT_INST(I_MOVW);
1.1291 if( sh4_x86.in_delay_slot ) {
1.1292 SLOTILLEGAL();
1.1293 } else {
1.1294 @@ -2534,6 +2701,7 @@
1.1295 case 0xA:
1.1296 { /* BRA disp */
1.1297 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1.1298 + COUNT_INST(I_BRA);
1.1299 if( sh4_x86.in_delay_slot ) {
1.1300 SLOTILLEGAL();
1.1301 } else {
1.1302 @@ -2556,6 +2724,7 @@
1.1303 case 0xB:
1.1304 { /* BSR disp */
1.1305 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1.1306 + COUNT_INST(I_BSR);
1.1307 if( sh4_x86.in_delay_slot ) {
1.1308 SLOTILLEGAL();
1.1309 } else {
1.1310 @@ -2583,6 +2752,7 @@
1.1311 case 0x0:
1.1312 { /* MOV.B R0, @(disp, GBR) */
1.1313 uint32_t disp = (ir&0xFF);
1.1314 + COUNT_INST(I_MOVB);
1.1315 load_spreg( R_EAX, R_GBR );
1.1316 ADD_imm32_r32( disp, R_EAX );
1.1317 MMU_TRANSLATE_WRITE( R_EAX );
1.1318 @@ -2594,6 +2764,7 @@
1.1319 case 0x1:
1.1320 { /* MOV.W R0, @(disp, GBR) */
1.1321 uint32_t disp = (ir&0xFF)<<1;
1.1322 + COUNT_INST(I_MOVW);
1.1323 load_spreg( R_EAX, R_GBR );
1.1324 ADD_imm32_r32( disp, R_EAX );
1.1325 check_walign16( R_EAX );
1.1326 @@ -2606,6 +2777,7 @@
1.1327 case 0x2:
1.1328 { /* MOV.L R0, @(disp, GBR) */
1.1329 uint32_t disp = (ir&0xFF)<<2;
1.1330 + COUNT_INST(I_MOVL);
1.1331 load_spreg( R_EAX, R_GBR );
1.1332 ADD_imm32_r32( disp, R_EAX );
1.1333 check_walign32( R_EAX );
1.1334 @@ -2618,6 +2790,7 @@
1.1335 case 0x3:
1.1336 { /* TRAPA #imm */
1.1337 uint32_t imm = (ir&0xFF);
1.1338 + COUNT_INST(I_TRAPA);
1.1339 if( sh4_x86.in_delay_slot ) {
1.1340 SLOTILLEGAL();
1.1341 } else {
1.1342 @@ -2635,6 +2808,7 @@
1.1343 case 0x4:
1.1344 { /* MOV.B @(disp, GBR), R0 */
1.1345 uint32_t disp = (ir&0xFF);
1.1346 + COUNT_INST(I_MOVB);
1.1347 load_spreg( R_EAX, R_GBR );
1.1348 ADD_imm32_r32( disp, R_EAX );
1.1349 MMU_TRANSLATE_READ( R_EAX );
1.1350 @@ -2646,6 +2820,7 @@
1.1351 case 0x5:
1.1352 { /* MOV.W @(disp, GBR), R0 */
1.1353 uint32_t disp = (ir&0xFF)<<1;
1.1354 + COUNT_INST(I_MOVW);
1.1355 load_spreg( R_EAX, R_GBR );
1.1356 ADD_imm32_r32( disp, R_EAX );
1.1357 check_ralign16( R_EAX );
1.1358 @@ -2658,6 +2833,7 @@
1.1359 case 0x6:
1.1360 { /* MOV.L @(disp, GBR), R0 */
1.1361 uint32_t disp = (ir&0xFF)<<2;
1.1362 + COUNT_INST(I_MOVL);
1.1363 load_spreg( R_EAX, R_GBR );
1.1364 ADD_imm32_r32( disp, R_EAX );
1.1365 check_ralign32( R_EAX );
1.1366 @@ -2670,6 +2846,7 @@
1.1367 case 0x7:
1.1368 { /* MOVA @(disp, PC), R0 */
1.1369 uint32_t disp = (ir&0xFF)<<2;
1.1370 + COUNT_INST(I_MOVA);
1.1371 if( sh4_x86.in_delay_slot ) {
1.1372 SLOTILLEGAL();
1.1373 } else {
1.1374 @@ -2683,6 +2860,7 @@
1.1375 case 0x8:
1.1376 { /* TST #imm, R0 */
1.1377 uint32_t imm = (ir&0xFF);
1.1378 + COUNT_INST(I_TSTI);
1.1379 load_reg( R_EAX, 0 );
1.1380 TEST_imm32_r32( imm, R_EAX );
1.1381 SETE_t();
1.1382 @@ -2692,6 +2870,7 @@
1.1383 case 0x9:
1.1384 { /* AND #imm, R0 */
1.1385 uint32_t imm = (ir&0xFF);
1.1386 + COUNT_INST(I_ANDI);
1.1387 load_reg( R_EAX, 0 );
1.1388 AND_imm32_r32(imm, R_EAX);
1.1389 store_reg( R_EAX, 0 );
1.1390 @@ -2701,6 +2880,7 @@
1.1391 case 0xA:
1.1392 { /* XOR #imm, R0 */
1.1393 uint32_t imm = (ir&0xFF);
1.1394 + COUNT_INST(I_XORI);
1.1395 load_reg( R_EAX, 0 );
1.1396 XOR_imm32_r32( imm, R_EAX );
1.1397 store_reg( R_EAX, 0 );
1.1398 @@ -2710,6 +2890,7 @@
1.1399 case 0xB:
1.1400 { /* OR #imm, R0 */
1.1401 uint32_t imm = (ir&0xFF);
1.1402 + COUNT_INST(I_ORI);
1.1403 load_reg( R_EAX, 0 );
1.1404 OR_imm32_r32(imm, R_EAX);
1.1405 store_reg( R_EAX, 0 );
1.1406 @@ -2719,6 +2900,7 @@
1.1407 case 0xC:
1.1408 { /* TST.B #imm, @(R0, GBR) */
1.1409 uint32_t imm = (ir&0xFF);
1.1410 + COUNT_INST(I_TSTB);
1.1411 load_reg( R_EAX, 0);
1.1412 load_reg( R_ECX, R_GBR);
1.1413 ADD_r32_r32( R_ECX, R_EAX );
1.1414 @@ -2732,6 +2914,7 @@
1.1415 case 0xD:
1.1416 { /* AND.B #imm, @(R0, GBR) */
1.1417 uint32_t imm = (ir&0xFF);
1.1418 + COUNT_INST(I_ANDB);
1.1419 load_reg( R_EAX, 0 );
1.1420 load_spreg( R_ECX, R_GBR );
1.1421 ADD_r32_r32( R_ECX, R_EAX );
1.1422 @@ -2747,6 +2930,7 @@
1.1423 case 0xE:
1.1424 { /* XOR.B #imm, @(R0, GBR) */
1.1425 uint32_t imm = (ir&0xFF);
1.1426 + COUNT_INST(I_XORB);
1.1427 load_reg( R_EAX, 0 );
1.1428 load_spreg( R_ECX, R_GBR );
1.1429 ADD_r32_r32( R_ECX, R_EAX );
1.1430 @@ -2762,6 +2946,7 @@
1.1431 case 0xF:
1.1432 { /* OR.B #imm, @(R0, GBR) */
1.1433 uint32_t imm = (ir&0xFF);
1.1434 + COUNT_INST(I_ORB);
1.1435 load_reg( R_EAX, 0 );
1.1436 load_spreg( R_ECX, R_GBR );
1.1437 ADD_r32_r32( R_ECX, R_EAX );
1.1438 @@ -2779,6 +2964,7 @@
1.1439 case 0xD:
1.1440 { /* MOV.L @(disp, PC), Rn */
1.1441 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
1.1442 + COUNT_INST(I_MOVLPC);
1.1443 if( sh4_x86.in_delay_slot ) {
1.1444 SLOTILLEGAL();
1.1445 } else {
1.1446 @@ -2812,6 +2998,7 @@
1.1447 case 0xE:
1.1448 { /* MOV #imm, Rn */
1.1449 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1.1450 + COUNT_INST(I_MOVI);
1.1451 load_imm32( R_EAX, imm );
1.1452 store_reg( R_EAX, Rn );
1.1453 }
1.1454 @@ -2821,6 +3008,7 @@
1.1455 case 0x0:
1.1456 { /* FADD FRm, FRn */
1.1457 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1458 + COUNT_INST(I_FADD);
1.1459 check_fpuen();
1.1460 load_spreg( R_ECX, R_FPSCR );
1.1461 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1462 @@ -2842,6 +3030,7 @@
1.1463 case 0x1:
1.1464 { /* FSUB FRm, FRn */
1.1465 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1466 + COUNT_INST(I_FSUB);
1.1467 check_fpuen();
1.1468 load_spreg( R_ECX, R_FPSCR );
1.1469 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1470 @@ -2863,6 +3052,7 @@
1.1471 case 0x2:
1.1472 { /* FMUL FRm, FRn */
1.1473 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1474 + COUNT_INST(I_FMUL);
1.1475 check_fpuen();
1.1476 load_spreg( R_ECX, R_FPSCR );
1.1477 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1478 @@ -2884,6 +3074,7 @@
1.1479 case 0x3:
1.1480 { /* FDIV FRm, FRn */
1.1481 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1482 + COUNT_INST(I_FDIV);
1.1483 check_fpuen();
1.1484 load_spreg( R_ECX, R_FPSCR );
1.1485 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1486 @@ -2905,6 +3096,7 @@
1.1487 case 0x4:
1.1488 { /* FCMP/EQ FRm, FRn */
1.1489 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1490 + COUNT_INST(I_FCMPEQ);
1.1491 check_fpuen();
1.1492 load_spreg( R_ECX, R_FPSCR );
1.1493 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1494 @@ -2925,6 +3117,7 @@
1.1495 case 0x5:
1.1496 { /* FCMP/GT FRm, FRn */
1.1497 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1498 + COUNT_INST(I_FCMPGT);
1.1499 check_fpuen();
1.1500 load_spreg( R_ECX, R_FPSCR );
1.1501 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1502 @@ -2945,6 +3138,7 @@
1.1503 case 0x6:
1.1504 { /* FMOV @(R0, Rm), FRn */
1.1505 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1506 + COUNT_INST(I_FMOV7);
1.1507 check_fpuen();
1.1508 load_reg( R_EAX, Rm );
1.1509 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
1.1510 @@ -2970,6 +3164,7 @@
1.1511 case 0x7:
1.1512 { /* FMOV FRm, @(R0, Rn) */
1.1513 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1514 + COUNT_INST(I_FMOV4);
1.1515 check_fpuen();
1.1516 load_reg( R_EAX, Rn );
1.1517 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
1.1518 @@ -2995,6 +3190,7 @@
1.1519 case 0x8:
1.1520 { /* FMOV @Rm, FRn */
1.1521 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1522 + COUNT_INST(I_FMOV5);
1.1523 check_fpuen();
1.1524 load_reg( R_EAX, Rm );
1.1525 check_ralign32( R_EAX );
1.1526 @@ -3018,6 +3214,7 @@
1.1527 case 0x9:
1.1528 { /* FMOV @Rm+, FRn */
1.1529 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1530 + COUNT_INST(I_FMOV6);
1.1531 check_fpuen();
1.1532 load_reg( R_EAX, Rm );
1.1533 check_ralign32( R_EAX );
1.1534 @@ -3044,6 +3241,7 @@
1.1535 case 0xA:
1.1536 { /* FMOV FRm, @Rn */
1.1537 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1538 + COUNT_INST(I_FMOV2);
1.1539 check_fpuen();
1.1540 load_reg( R_EAX, Rn );
1.1541 check_walign32( R_EAX );
1.1542 @@ -3067,6 +3265,7 @@
1.1543 case 0xB:
1.1544 { /* FMOV FRm, @-Rn */
1.1545 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1546 + COUNT_INST(I_FMOV3);
1.1547 check_fpuen();
1.1548 load_reg( R_EAX, Rn );
1.1549 check_walign32( R_EAX );
1.1550 @@ -3096,6 +3295,7 @@
1.1551 case 0xC:
1.1552 { /* FMOV FRm, FRn */
1.1553 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1554 + COUNT_INST(I_FMOV1);
1.1555 /* As horrible as this looks, it's actually covering 5 separate cases:
1.1556 * 1. 32-bit fr-to-fr (PR=0)
1.1557 * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
1.1558 @@ -3124,6 +3324,7 @@
1.1559 case 0x0:
1.1560 { /* FSTS FPUL, FRn */
1.1561 uint32_t FRn = ((ir>>8)&0xF);
1.1562 + COUNT_INST(I_FSTS);
1.1563 check_fpuen();
1.1564 load_spreg( R_EAX, R_FPUL );
1.1565 store_fr( R_EAX, FRn );
1.1566 @@ -3133,6 +3334,7 @@
1.1567 case 0x1:
1.1568 { /* FLDS FRm, FPUL */
1.1569 uint32_t FRm = ((ir>>8)&0xF);
1.1570 + COUNT_INST(I_FLDS);
1.1571 check_fpuen();
1.1572 load_fr( R_EAX, FRm );
1.1573 store_spreg( R_EAX, R_FPUL );
1.1574 @@ -3142,6 +3344,7 @@
1.1575 case 0x2:
1.1576 { /* FLOAT FPUL, FRn */
1.1577 uint32_t FRn = ((ir>>8)&0xF);
1.1578 + COUNT_INST(I_FLOAT);
1.1579 check_fpuen();
1.1580 load_spreg( R_ECX, R_FPSCR );
1.1581 FILD_sh4r(R_FPUL);
1.1582 @@ -3158,6 +3361,7 @@
1.1583 case 0x3:
1.1584 { /* FTRC FRm, FPUL */
1.1585 uint32_t FRm = ((ir>>8)&0xF);
1.1586 + COUNT_INST(I_FTRC);
1.1587 check_fpuen();
1.1588 load_spreg( R_ECX, R_FPSCR );
1.1589 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1590 @@ -3195,6 +3399,7 @@
1.1591 case 0x4:
1.1592 { /* FNEG FRn */
1.1593 uint32_t FRn = ((ir>>8)&0xF);
1.1594 + COUNT_INST(I_FNEG);
1.1595 check_fpuen();
1.1596 load_spreg( R_ECX, R_FPSCR );
1.1597 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1598 @@ -3214,6 +3419,7 @@
1.1599 case 0x5:
1.1600 { /* FABS FRn */
1.1601 uint32_t FRn = ((ir>>8)&0xF);
1.1602 + COUNT_INST(I_FABS);
1.1603 check_fpuen();
1.1604 load_spreg( R_ECX, R_FPSCR );
1.1605 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1606 @@ -3233,6 +3439,7 @@
1.1607 case 0x6:
1.1608 { /* FSQRT FRn */
1.1609 uint32_t FRn = ((ir>>8)&0xF);
1.1610 + COUNT_INST(I_FSQRT);
1.1611 check_fpuen();
1.1612 load_spreg( R_ECX, R_FPSCR );
1.1613 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1614 @@ -3252,6 +3459,7 @@
1.1615 case 0x7:
1.1616 { /* FSRRA FRn */
1.1617 uint32_t FRn = ((ir>>8)&0xF);
1.1618 + COUNT_INST(I_FSRRA);
1.1619 check_fpuen();
1.1620 load_spreg( R_ECX, R_FPSCR );
1.1621 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1622 @@ -3269,6 +3477,7 @@
1.1623 { /* FLDI0 FRn */
1.1624 uint32_t FRn = ((ir>>8)&0xF);
1.1625 /* IFF PR=0 */
1.1626 + COUNT_INST(I_FLDI0);
1.1627 check_fpuen();
1.1628 load_spreg( R_ECX, R_FPSCR );
1.1629 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1630 @@ -3283,6 +3492,7 @@
1.1631 { /* FLDI1 FRn */
1.1632 uint32_t FRn = ((ir>>8)&0xF);
1.1633 /* IFF PR=0 */
1.1634 + COUNT_INST(I_FLDI1);
1.1635 check_fpuen();
1.1636 load_spreg( R_ECX, R_FPSCR );
1.1637 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1638 @@ -3296,6 +3506,7 @@
1.1639 case 0xA:
1.1640 { /* FCNVSD FPUL, FRn */
1.1641 uint32_t FRn = ((ir>>8)&0xF);
1.1642 + COUNT_INST(I_FCNVSD);
1.1643 check_fpuen();
1.1644 load_spreg( R_ECX, R_FPSCR );
1.1645 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1646 @@ -3309,6 +3520,7 @@
1.1647 case 0xB:
1.1648 { /* FCNVDS FRm, FPUL */
1.1649 uint32_t FRm = ((ir>>8)&0xF);
1.1650 + COUNT_INST(I_FCNVDS);
1.1651 check_fpuen();
1.1652 load_spreg( R_ECX, R_FPSCR );
1.1653 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1654 @@ -3322,6 +3534,7 @@
1.1655 case 0xE:
1.1656 { /* FIPR FVm, FVn */
1.1657 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
1.1658 + COUNT_INST(I_FIPR);
1.1659 check_fpuen();
1.1660 load_spreg( R_ECX, R_FPSCR );
1.1661 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1662 @@ -3352,6 +3565,7 @@
1.1663 case 0x0:
1.1664 { /* FSCA FPUL, FRn */
1.1665 uint32_t FRn = ((ir>>9)&0x7)<<1;
1.1666 + COUNT_INST(I_FSCA);
1.1667 check_fpuen();
1.1668 load_spreg( R_ECX, R_FPSCR );
1.1669 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1670 @@ -3368,6 +3582,7 @@
1.1671 case 0x0:
1.1672 { /* FTRV XMTRX, FVn */
1.1673 uint32_t FVn = ((ir>>10)&0x3);
1.1674 + COUNT_INST(I_FTRV);
1.1675 check_fpuen();
1.1676 load_spreg( R_ECX, R_FPSCR );
1.1677 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1678 @@ -3382,6 +3597,7 @@
1.1679 switch( (ir&0xC00) >> 10 ) {
1.1680 case 0x0:
1.1681 { /* FSCHG */
1.1682 + COUNT_INST(I_FSCHG);
1.1683 check_fpuen();
1.1684 load_spreg( R_ECX, R_FPSCR );
1.1685 XOR_imm32_r32( FPSCR_SZ, R_ECX );
1.1686 @@ -3391,6 +3607,7 @@
1.1687 break;
1.1688 case 0x2:
1.1689 { /* FRCHG */
1.1690 + COUNT_INST(I_FRCHG);
1.1691 check_fpuen();
1.1692 load_spreg( R_ECX, R_FPSCR );
1.1693 XOR_imm32_r32( FPSCR_FR, R_ECX );
1.1694 @@ -3401,6 +3618,7 @@
1.1695 break;
1.1696 case 0x3:
1.1697 { /* UNDEF */
1.1698 + COUNT_INST(I_UNDEF);
1.1699 if( sh4_x86.in_delay_slot ) {
1.1700 SLOTILLEGAL();
1.1701 } else {
1.1702 @@ -3426,6 +3644,7 @@
1.1703 case 0xE:
1.1704 { /* FMAC FR0, FRm, FRn */
1.1705 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1706 + COUNT_INST(I_FMAC);
1.1707 check_fpuen();
1.1708 load_spreg( R_ECX, R_FPSCR );
1.1709 TEST_imm32_r32( FPSCR_PR, R_ECX );
.