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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 671:a530ea88eebd
prev669:ab344e42bca9
next673:44c579439d73
author nkeynes
date Thu May 15 10:22:39 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Permanently add SH4 instruction statistics tracking (enabled with --enable-sh4stats)
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Mon May 12 10:00:13 2008 +0000
1.2 +++ b/src/sh4/sh4x86.in Thu May 15 10:22:39 2008 +0000
1.3 @@ -28,6 +28,7 @@
1.4 #include "sh4/xltcache.h"
1.5 #include "sh4/sh4core.h"
1.6 #include "sh4/sh4trans.h"
1.7 +#include "sh4/sh4stat.h"
1.8 #include "sh4/sh4mmio.h"
1.9 #include "sh4/x86op.h"
1.10 #include "clock.h"
1.11 @@ -79,6 +80,12 @@
1.12 #define TSTATE_A 7
1.13 #define TSTATE_AE 3
1.14
1.15 +#ifdef ENABLE_SH4STATS
1.16 +#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
1.17 +#else
1.18 +#define COUNT_INST(id)
1.19 +#endif
1.20 +
1.21 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
1.22 #define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
1.23 CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
1.24 @@ -384,6 +391,7 @@
1.25 %%
1.26 /* ALU operations */
1.27 ADD Rm, Rn {:
1.28 + COUNT_INST(I_ADD);
1.29 load_reg( R_EAX, Rm );
1.30 load_reg( R_ECX, Rn );
1.31 ADD_r32_r32( R_EAX, R_ECX );
1.32 @@ -391,12 +399,14 @@
1.33 sh4_x86.tstate = TSTATE_NONE;
1.34 :}
1.35 ADD #imm, Rn {:
1.36 + COUNT_INST(I_ADDI);
1.37 load_reg( R_EAX, Rn );
1.38 ADD_imm8s_r32( imm, R_EAX );
1.39 store_reg( R_EAX, Rn );
1.40 sh4_x86.tstate = TSTATE_NONE;
1.41 :}
1.42 ADDC Rm, Rn {:
1.43 + COUNT_INST(I_ADDC);
1.44 if( sh4_x86.tstate != TSTATE_C ) {
1.45 LDC_t();
1.46 }
1.47 @@ -408,6 +418,7 @@
1.48 sh4_x86.tstate = TSTATE_C;
1.49 :}
1.50 ADDV Rm, Rn {:
1.51 + COUNT_INST(I_ADDV);
1.52 load_reg( R_EAX, Rm );
1.53 load_reg( R_ECX, Rn );
1.54 ADD_r32_r32( R_EAX, R_ECX );
1.55 @@ -416,6 +427,7 @@
1.56 sh4_x86.tstate = TSTATE_O;
1.57 :}
1.58 AND Rm, Rn {:
1.59 + COUNT_INST(I_AND);
1.60 load_reg( R_EAX, Rm );
1.61 load_reg( R_ECX, Rn );
1.62 AND_r32_r32( R_EAX, R_ECX );
1.63 @@ -423,12 +435,14 @@
1.64 sh4_x86.tstate = TSTATE_NONE;
1.65 :}
1.66 AND #imm, R0 {:
1.67 + COUNT_INST(I_ANDI);
1.68 load_reg( R_EAX, 0 );
1.69 AND_imm32_r32(imm, R_EAX);
1.70 store_reg( R_EAX, 0 );
1.71 sh4_x86.tstate = TSTATE_NONE;
1.72 :}
1.73 AND.B #imm, @(R0, GBR) {:
1.74 + COUNT_INST(I_ANDB);
1.75 load_reg( R_EAX, 0 );
1.76 load_spreg( R_ECX, R_GBR );
1.77 ADD_r32_r32( R_ECX, R_EAX );
1.78 @@ -441,6 +455,7 @@
1.79 sh4_x86.tstate = TSTATE_NONE;
1.80 :}
1.81 CMP/EQ Rm, Rn {:
1.82 + COUNT_INST(I_CMPEQ);
1.83 load_reg( R_EAX, Rm );
1.84 load_reg( R_ECX, Rn );
1.85 CMP_r32_r32( R_EAX, R_ECX );
1.86 @@ -448,12 +463,14 @@
1.87 sh4_x86.tstate = TSTATE_E;
1.88 :}
1.89 CMP/EQ #imm, R0 {:
1.90 + COUNT_INST(I_CMPEQI);
1.91 load_reg( R_EAX, 0 );
1.92 CMP_imm8s_r32(imm, R_EAX);
1.93 SETE_t();
1.94 sh4_x86.tstate = TSTATE_E;
1.95 :}
1.96 CMP/GE Rm, Rn {:
1.97 + COUNT_INST(I_CMPGE);
1.98 load_reg( R_EAX, Rm );
1.99 load_reg( R_ECX, Rn );
1.100 CMP_r32_r32( R_EAX, R_ECX );
1.101 @@ -461,6 +478,7 @@
1.102 sh4_x86.tstate = TSTATE_GE;
1.103 :}
1.104 CMP/GT Rm, Rn {:
1.105 + COUNT_INST(I_CMPGT);
1.106 load_reg( R_EAX, Rm );
1.107 load_reg( R_ECX, Rn );
1.108 CMP_r32_r32( R_EAX, R_ECX );
1.109 @@ -468,6 +486,7 @@
1.110 sh4_x86.tstate = TSTATE_G;
1.111 :}
1.112 CMP/HI Rm, Rn {:
1.113 + COUNT_INST(I_CMPHI);
1.114 load_reg( R_EAX, Rm );
1.115 load_reg( R_ECX, Rn );
1.116 CMP_r32_r32( R_EAX, R_ECX );
1.117 @@ -475,6 +494,7 @@
1.118 sh4_x86.tstate = TSTATE_A;
1.119 :}
1.120 CMP/HS Rm, Rn {:
1.121 + COUNT_INST(I_CMPHS);
1.122 load_reg( R_EAX, Rm );
1.123 load_reg( R_ECX, Rn );
1.124 CMP_r32_r32( R_EAX, R_ECX );
1.125 @@ -482,18 +502,21 @@
1.126 sh4_x86.tstate = TSTATE_AE;
1.127 :}
1.128 CMP/PL Rn {:
1.129 + COUNT_INST(I_CMPPL);
1.130 load_reg( R_EAX, Rn );
1.131 CMP_imm8s_r32( 0, R_EAX );
1.132 SETG_t();
1.133 sh4_x86.tstate = TSTATE_G;
1.134 :}
1.135 CMP/PZ Rn {:
1.136 + COUNT_INST(I_CMPPZ);
1.137 load_reg( R_EAX, Rn );
1.138 CMP_imm8s_r32( 0, R_EAX );
1.139 SETGE_t();
1.140 sh4_x86.tstate = TSTATE_GE;
1.141 :}
1.142 CMP/STR Rm, Rn {:
1.143 + COUNT_INST(I_CMPSTR);
1.144 load_reg( R_EAX, Rm );
1.145 load_reg( R_ECX, Rn );
1.146 XOR_r32_r32( R_ECX, R_EAX );
1.147 @@ -512,6 +535,7 @@
1.148 sh4_x86.tstate = TSTATE_E;
1.149 :}
1.150 DIV0S Rm, Rn {:
1.151 + COUNT_INST(I_DIV0S);
1.152 load_reg( R_EAX, Rm );
1.153 load_reg( R_ECX, Rn );
1.154 SHR_imm8_r32( 31, R_EAX );
1.155 @@ -523,6 +547,7 @@
1.156 sh4_x86.tstate = TSTATE_NE;
1.157 :}
1.158 DIV0U {:
1.159 + COUNT_INST(I_DIV0U);
1.160 XOR_r32_r32( R_EAX, R_EAX );
1.161 store_spreg( R_EAX, R_Q );
1.162 store_spreg( R_EAX, R_M );
1.163 @@ -530,6 +555,7 @@
1.164 sh4_x86.tstate = TSTATE_C; // works for DIV1
1.165 :}
1.166 DIV1 Rm, Rn {:
1.167 + COUNT_INST(I_DIV1);
1.168 load_spreg( R_ECX, R_M );
1.169 load_reg( R_EAX, Rn );
1.170 if( sh4_x86.tstate != TSTATE_C ) {
1.171 @@ -555,6 +581,7 @@
1.172 sh4_x86.tstate = TSTATE_NONE;
1.173 :}
1.174 DMULS.L Rm, Rn {:
1.175 + COUNT_INST(I_DMULS);
1.176 load_reg( R_EAX, Rm );
1.177 load_reg( R_ECX, Rn );
1.178 IMUL_r32(R_ECX);
1.179 @@ -563,6 +590,7 @@
1.180 sh4_x86.tstate = TSTATE_NONE;
1.181 :}
1.182 DMULU.L Rm, Rn {:
1.183 + COUNT_INST(I_DMULU);
1.184 load_reg( R_EAX, Rm );
1.185 load_reg( R_ECX, Rn );
1.186 MUL_r32(R_ECX);
1.187 @@ -571,6 +599,7 @@
1.188 sh4_x86.tstate = TSTATE_NONE;
1.189 :}
1.190 DT Rn {:
1.191 + COUNT_INST(I_DT);
1.192 load_reg( R_EAX, Rn );
1.193 ADD_imm8s_r32( -1, R_EAX );
1.194 store_reg( R_EAX, Rn );
1.195 @@ -578,26 +607,31 @@
1.196 sh4_x86.tstate = TSTATE_E;
1.197 :}
1.198 EXTS.B Rm, Rn {:
1.199 + COUNT_INST(I_EXTSB);
1.200 load_reg( R_EAX, Rm );
1.201 MOVSX_r8_r32( R_EAX, R_EAX );
1.202 store_reg( R_EAX, Rn );
1.203 :}
1.204 EXTS.W Rm, Rn {:
1.205 + COUNT_INST(I_EXTSW);
1.206 load_reg( R_EAX, Rm );
1.207 MOVSX_r16_r32( R_EAX, R_EAX );
1.208 store_reg( R_EAX, Rn );
1.209 :}
1.210 EXTU.B Rm, Rn {:
1.211 + COUNT_INST(I_EXTUB);
1.212 load_reg( R_EAX, Rm );
1.213 MOVZX_r8_r32( R_EAX, R_EAX );
1.214 store_reg( R_EAX, Rn );
1.215 :}
1.216 EXTU.W Rm, Rn {:
1.217 + COUNT_INST(I_EXTUW);
1.218 load_reg( R_EAX, Rm );
1.219 MOVZX_r16_r32( R_EAX, R_EAX );
1.220 store_reg( R_EAX, Rn );
1.221 :}
1.222 MAC.L @Rm+, @Rn+ {:
1.223 + COUNT_INST(I_MACL);
1.224 if( Rm == Rn ) {
1.225 load_reg( R_EAX, Rm );
1.226 check_ralign32( R_EAX );
1.227 @@ -639,6 +673,7 @@
1.228 sh4_x86.tstate = TSTATE_NONE;
1.229 :}
1.230 MAC.W @Rm+, @Rn+ {:
1.231 + COUNT_INST(I_MACW);
1.232 if( Rm == Rn ) {
1.233 load_reg( R_EAX, Rm );
1.234 check_ralign16( R_EAX );
1.235 @@ -696,10 +731,12 @@
1.236 sh4_x86.tstate = TSTATE_NONE;
1.237 :}
1.238 MOVT Rn {:
1.239 + COUNT_INST(I_MOVT);
1.240 load_spreg( R_EAX, R_T );
1.241 store_reg( R_EAX, Rn );
1.242 :}
1.243 MUL.L Rm, Rn {:
1.244 + COUNT_INST(I_MULL);
1.245 load_reg( R_EAX, Rm );
1.246 load_reg( R_ECX, Rn );
1.247 MUL_r32( R_ECX );
1.248 @@ -707,6 +744,7 @@
1.249 sh4_x86.tstate = TSTATE_NONE;
1.250 :}
1.251 MULS.W Rm, Rn {:
1.252 + COUNT_INST(I_MULSW);
1.253 load_reg16s( R_EAX, Rm );
1.254 load_reg16s( R_ECX, Rn );
1.255 MUL_r32( R_ECX );
1.256 @@ -714,6 +752,7 @@
1.257 sh4_x86.tstate = TSTATE_NONE;
1.258 :}
1.259 MULU.W Rm, Rn {:
1.260 + COUNT_INST(I_MULUW);
1.261 load_reg16u( R_EAX, Rm );
1.262 load_reg16u( R_ECX, Rn );
1.263 MUL_r32( R_ECX );
1.264 @@ -721,12 +760,14 @@
1.265 sh4_x86.tstate = TSTATE_NONE;
1.266 :}
1.267 NEG Rm, Rn {:
1.268 + COUNT_INST(I_NEG);
1.269 load_reg( R_EAX, Rm );
1.270 NEG_r32( R_EAX );
1.271 store_reg( R_EAX, Rn );
1.272 sh4_x86.tstate = TSTATE_NONE;
1.273 :}
1.274 NEGC Rm, Rn {:
1.275 + COUNT_INST(I_NEGC);
1.276 load_reg( R_EAX, Rm );
1.277 XOR_r32_r32( R_ECX, R_ECX );
1.278 LDC_t();
1.279 @@ -736,12 +777,14 @@
1.280 sh4_x86.tstate = TSTATE_C;
1.281 :}
1.282 NOT Rm, Rn {:
1.283 + COUNT_INST(I_NOT);
1.284 load_reg( R_EAX, Rm );
1.285 NOT_r32( R_EAX );
1.286 store_reg( R_EAX, Rn );
1.287 sh4_x86.tstate = TSTATE_NONE;
1.288 :}
1.289 OR Rm, Rn {:
1.290 + COUNT_INST(I_OR);
1.291 load_reg( R_EAX, Rm );
1.292 load_reg( R_ECX, Rn );
1.293 OR_r32_r32( R_EAX, R_ECX );
1.294 @@ -749,12 +792,14 @@
1.295 sh4_x86.tstate = TSTATE_NONE;
1.296 :}
1.297 OR #imm, R0 {:
1.298 + COUNT_INST(I_ORI);
1.299 load_reg( R_EAX, 0 );
1.300 OR_imm32_r32(imm, R_EAX);
1.301 store_reg( R_EAX, 0 );
1.302 sh4_x86.tstate = TSTATE_NONE;
1.303 :}
1.304 OR.B #imm, @(R0, GBR) {:
1.305 + COUNT_INST(I_ORB);
1.306 load_reg( R_EAX, 0 );
1.307 load_spreg( R_ECX, R_GBR );
1.308 ADD_r32_r32( R_ECX, R_EAX );
1.309 @@ -767,6 +812,7 @@
1.310 sh4_x86.tstate = TSTATE_NONE;
1.311 :}
1.312 ROTCL Rn {:
1.313 + COUNT_INST(I_ROTCL);
1.314 load_reg( R_EAX, Rn );
1.315 if( sh4_x86.tstate != TSTATE_C ) {
1.316 LDC_t();
1.317 @@ -777,6 +823,7 @@
1.318 sh4_x86.tstate = TSTATE_C;
1.319 :}
1.320 ROTCR Rn {:
1.321 + COUNT_INST(I_ROTCR);
1.322 load_reg( R_EAX, Rn );
1.323 if( sh4_x86.tstate != TSTATE_C ) {
1.324 LDC_t();
1.325 @@ -787,6 +834,7 @@
1.326 sh4_x86.tstate = TSTATE_C;
1.327 :}
1.328 ROTL Rn {:
1.329 + COUNT_INST(I_ROTL);
1.330 load_reg( R_EAX, Rn );
1.331 ROL1_r32( R_EAX );
1.332 store_reg( R_EAX, Rn );
1.333 @@ -794,6 +842,7 @@
1.334 sh4_x86.tstate = TSTATE_C;
1.335 :}
1.336 ROTR Rn {:
1.337 + COUNT_INST(I_ROTR);
1.338 load_reg( R_EAX, Rn );
1.339 ROR1_r32( R_EAX );
1.340 store_reg( R_EAX, Rn );
1.341 @@ -801,6 +850,7 @@
1.342 sh4_x86.tstate = TSTATE_C;
1.343 :}
1.344 SHAD Rm, Rn {:
1.345 + COUNT_INST(I_SHAD);
1.346 /* Annoyingly enough, not directly convertible */
1.347 load_reg( R_EAX, Rn );
1.348 load_reg( R_ECX, Rm );
1.349 @@ -826,6 +876,7 @@
1.350 sh4_x86.tstate = TSTATE_NONE;
1.351 :}
1.352 SHLD Rm, Rn {:
1.353 + COUNT_INST(I_SHLD);
1.354 load_reg( R_EAX, Rn );
1.355 load_reg( R_ECX, Rm );
1.356 CMP_imm32_r32( 0, R_ECX );
1.357 @@ -850,6 +901,7 @@
1.358 sh4_x86.tstate = TSTATE_NONE;
1.359 :}
1.360 SHAL Rn {:
1.361 + COUNT_INST(I_SHAL);
1.362 load_reg( R_EAX, Rn );
1.363 SHL1_r32( R_EAX );
1.364 SETC_t();
1.365 @@ -857,6 +909,7 @@
1.366 sh4_x86.tstate = TSTATE_C;
1.367 :}
1.368 SHAR Rn {:
1.369 + COUNT_INST(I_SHAR);
1.370 load_reg( R_EAX, Rn );
1.371 SAR1_r32( R_EAX );
1.372 SETC_t();
1.373 @@ -864,6 +917,7 @@
1.374 sh4_x86.tstate = TSTATE_C;
1.375 :}
1.376 SHLL Rn {:
1.377 + COUNT_INST(I_SHLL);
1.378 load_reg( R_EAX, Rn );
1.379 SHL1_r32( R_EAX );
1.380 SETC_t();
1.381 @@ -871,24 +925,28 @@
1.382 sh4_x86.tstate = TSTATE_C;
1.383 :}
1.384 SHLL2 Rn {:
1.385 + COUNT_INST(I_SHLL);
1.386 load_reg( R_EAX, Rn );
1.387 SHL_imm8_r32( 2, R_EAX );
1.388 store_reg( R_EAX, Rn );
1.389 sh4_x86.tstate = TSTATE_NONE;
1.390 :}
1.391 SHLL8 Rn {:
1.392 + COUNT_INST(I_SHLL);
1.393 load_reg( R_EAX, Rn );
1.394 SHL_imm8_r32( 8, R_EAX );
1.395 store_reg( R_EAX, Rn );
1.396 sh4_x86.tstate = TSTATE_NONE;
1.397 :}
1.398 SHLL16 Rn {:
1.399 + COUNT_INST(I_SHLL);
1.400 load_reg( R_EAX, Rn );
1.401 SHL_imm8_r32( 16, R_EAX );
1.402 store_reg( R_EAX, Rn );
1.403 sh4_x86.tstate = TSTATE_NONE;
1.404 :}
1.405 SHLR Rn {:
1.406 + COUNT_INST(I_SHLR);
1.407 load_reg( R_EAX, Rn );
1.408 SHR1_r32( R_EAX );
1.409 SETC_t();
1.410 @@ -896,24 +954,28 @@
1.411 sh4_x86.tstate = TSTATE_C;
1.412 :}
1.413 SHLR2 Rn {:
1.414 + COUNT_INST(I_SHLR);
1.415 load_reg( R_EAX, Rn );
1.416 SHR_imm8_r32( 2, R_EAX );
1.417 store_reg( R_EAX, Rn );
1.418 sh4_x86.tstate = TSTATE_NONE;
1.419 :}
1.420 SHLR8 Rn {:
1.421 + COUNT_INST(I_SHLR);
1.422 load_reg( R_EAX, Rn );
1.423 SHR_imm8_r32( 8, R_EAX );
1.424 store_reg( R_EAX, Rn );
1.425 sh4_x86.tstate = TSTATE_NONE;
1.426 :}
1.427 SHLR16 Rn {:
1.428 + COUNT_INST(I_SHLR);
1.429 load_reg( R_EAX, Rn );
1.430 SHR_imm8_r32( 16, R_EAX );
1.431 store_reg( R_EAX, Rn );
1.432 sh4_x86.tstate = TSTATE_NONE;
1.433 :}
1.434 SUB Rm, Rn {:
1.435 + COUNT_INST(I_SUB);
1.436 load_reg( R_EAX, Rm );
1.437 load_reg( R_ECX, Rn );
1.438 SUB_r32_r32( R_EAX, R_ECX );
1.439 @@ -921,6 +983,7 @@
1.440 sh4_x86.tstate = TSTATE_NONE;
1.441 :}
1.442 SUBC Rm, Rn {:
1.443 + COUNT_INST(I_SUBC);
1.444 load_reg( R_EAX, Rm );
1.445 load_reg( R_ECX, Rn );
1.446 if( sh4_x86.tstate != TSTATE_C ) {
1.447 @@ -932,6 +995,7 @@
1.448 sh4_x86.tstate = TSTATE_C;
1.449 :}
1.450 SUBV Rm, Rn {:
1.451 + COUNT_INST(I_SUBV);
1.452 load_reg( R_EAX, Rm );
1.453 load_reg( R_ECX, Rn );
1.454 SUB_r32_r32( R_EAX, R_ECX );
1.455 @@ -940,11 +1004,13 @@
1.456 sh4_x86.tstate = TSTATE_O;
1.457 :}
1.458 SWAP.B Rm, Rn {:
1.459 + COUNT_INST(I_SWAPB);
1.460 load_reg( R_EAX, Rm );
1.461 XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
1.462 store_reg( R_EAX, Rn );
1.463 :}
1.464 SWAP.W Rm, Rn {:
1.465 + COUNT_INST(I_SWAPB);
1.466 load_reg( R_EAX, Rm );
1.467 MOV_r32_r32( R_EAX, R_ECX );
1.468 SHL_imm8_r32( 16, R_ECX );
1.469 @@ -954,6 +1020,7 @@
1.470 sh4_x86.tstate = TSTATE_NONE;
1.471 :}
1.472 TAS.B @Rn {:
1.473 + COUNT_INST(I_TASB);
1.474 load_reg( R_EAX, Rn );
1.475 MMU_TRANSLATE_WRITE( R_EAX );
1.476 PUSH_realigned_r32( R_EAX );
1.477 @@ -966,6 +1033,7 @@
1.478 sh4_x86.tstate = TSTATE_NONE;
1.479 :}
1.480 TST Rm, Rn {:
1.481 + COUNT_INST(I_TST);
1.482 load_reg( R_EAX, Rm );
1.483 load_reg( R_ECX, Rn );
1.484 TEST_r32_r32( R_EAX, R_ECX );
1.485 @@ -973,12 +1041,14 @@
1.486 sh4_x86.tstate = TSTATE_E;
1.487 :}
1.488 TST #imm, R0 {:
1.489 + COUNT_INST(I_TSTI);
1.490 load_reg( R_EAX, 0 );
1.491 TEST_imm32_r32( imm, R_EAX );
1.492 SETE_t();
1.493 sh4_x86.tstate = TSTATE_E;
1.494 :}
1.495 TST.B #imm, @(R0, GBR) {:
1.496 + COUNT_INST(I_TSTB);
1.497 load_reg( R_EAX, 0);
1.498 load_reg( R_ECX, R_GBR);
1.499 ADD_r32_r32( R_ECX, R_EAX );
1.500 @@ -989,6 +1059,7 @@
1.501 sh4_x86.tstate = TSTATE_E;
1.502 :}
1.503 XOR Rm, Rn {:
1.504 + COUNT_INST(I_XOR);
1.505 load_reg( R_EAX, Rm );
1.506 load_reg( R_ECX, Rn );
1.507 XOR_r32_r32( R_EAX, R_ECX );
1.508 @@ -996,12 +1067,14 @@
1.509 sh4_x86.tstate = TSTATE_NONE;
1.510 :}
1.511 XOR #imm, R0 {:
1.512 + COUNT_INST(I_XORI);
1.513 load_reg( R_EAX, 0 );
1.514 XOR_imm32_r32( imm, R_EAX );
1.515 store_reg( R_EAX, 0 );
1.516 sh4_x86.tstate = TSTATE_NONE;
1.517 :}
1.518 XOR.B #imm, @(R0, GBR) {:
1.519 + COUNT_INST(I_XORB);
1.520 load_reg( R_EAX, 0 );
1.521 load_spreg( R_ECX, R_GBR );
1.522 ADD_r32_r32( R_ECX, R_EAX );
1.523 @@ -1014,6 +1087,7 @@
1.524 sh4_x86.tstate = TSTATE_NONE;
1.525 :}
1.526 XTRCT Rm, Rn {:
1.527 + COUNT_INST(I_XTRCT);
1.528 load_reg( R_EAX, Rm );
1.529 load_reg( R_ECX, Rn );
1.530 SHL_imm8_r32( 16, R_EAX );
1.531 @@ -1025,14 +1099,17 @@
1.532
1.533 /* Data move instructions */
1.534 MOV Rm, Rn {:
1.535 + COUNT_INST(I_MOV);
1.536 load_reg( R_EAX, Rm );
1.537 store_reg( R_EAX, Rn );
1.538 :}
1.539 MOV #imm, Rn {:
1.540 + COUNT_INST(I_MOVI);
1.541 load_imm32( R_EAX, imm );
1.542 store_reg( R_EAX, Rn );
1.543 :}
1.544 MOV.B Rm, @Rn {:
1.545 + COUNT_INST(I_MOVB);
1.546 load_reg( R_EAX, Rn );
1.547 MMU_TRANSLATE_WRITE( R_EAX );
1.548 load_reg( R_EDX, Rm );
1.549 @@ -1040,6 +1117,7 @@
1.550 sh4_x86.tstate = TSTATE_NONE;
1.551 :}
1.552 MOV.B Rm, @-Rn {:
1.553 + COUNT_INST(I_MOVB);
1.554 load_reg( R_EAX, Rn );
1.555 ADD_imm8s_r32( -1, R_EAX );
1.556 MMU_TRANSLATE_WRITE( R_EAX );
1.557 @@ -1049,6 +1127,7 @@
1.558 sh4_x86.tstate = TSTATE_NONE;
1.559 :}
1.560 MOV.B Rm, @(R0, Rn) {:
1.561 + COUNT_INST(I_MOVB);
1.562 load_reg( R_EAX, 0 );
1.563 load_reg( R_ECX, Rn );
1.564 ADD_r32_r32( R_ECX, R_EAX );
1.565 @@ -1058,6 +1137,7 @@
1.566 sh4_x86.tstate = TSTATE_NONE;
1.567 :}
1.568 MOV.B R0, @(disp, GBR) {:
1.569 + COUNT_INST(I_MOVB);
1.570 load_spreg( R_EAX, R_GBR );
1.571 ADD_imm32_r32( disp, R_EAX );
1.572 MMU_TRANSLATE_WRITE( R_EAX );
1.573 @@ -1066,6 +1146,7 @@
1.574 sh4_x86.tstate = TSTATE_NONE;
1.575 :}
1.576 MOV.B R0, @(disp, Rn) {:
1.577 + COUNT_INST(I_MOVB);
1.578 load_reg( R_EAX, Rn );
1.579 ADD_imm32_r32( disp, R_EAX );
1.580 MMU_TRANSLATE_WRITE( R_EAX );
1.581 @@ -1074,6 +1155,7 @@
1.582 sh4_x86.tstate = TSTATE_NONE;
1.583 :}
1.584 MOV.B @Rm, Rn {:
1.585 + COUNT_INST(I_MOVB);
1.586 load_reg( R_EAX, Rm );
1.587 MMU_TRANSLATE_READ( R_EAX );
1.588 MEM_READ_BYTE( R_EAX, R_EAX );
1.589 @@ -1081,6 +1163,7 @@
1.590 sh4_x86.tstate = TSTATE_NONE;
1.591 :}
1.592 MOV.B @Rm+, Rn {:
1.593 + COUNT_INST(I_MOVB);
1.594 load_reg( R_EAX, Rm );
1.595 MMU_TRANSLATE_READ( R_EAX );
1.596 ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
1.597 @@ -1089,6 +1172,7 @@
1.598 sh4_x86.tstate = TSTATE_NONE;
1.599 :}
1.600 MOV.B @(R0, Rm), Rn {:
1.601 + COUNT_INST(I_MOVB);
1.602 load_reg( R_EAX, 0 );
1.603 load_reg( R_ECX, Rm );
1.604 ADD_r32_r32( R_ECX, R_EAX );
1.605 @@ -1098,6 +1182,7 @@
1.606 sh4_x86.tstate = TSTATE_NONE;
1.607 :}
1.608 MOV.B @(disp, GBR), R0 {:
1.609 + COUNT_INST(I_MOVB);
1.610 load_spreg( R_EAX, R_GBR );
1.611 ADD_imm32_r32( disp, R_EAX );
1.612 MMU_TRANSLATE_READ( R_EAX );
1.613 @@ -1106,6 +1191,7 @@
1.614 sh4_x86.tstate = TSTATE_NONE;
1.615 :}
1.616 MOV.B @(disp, Rm), R0 {:
1.617 + COUNT_INST(I_MOVB);
1.618 load_reg( R_EAX, Rm );
1.619 ADD_imm32_r32( disp, R_EAX );
1.620 MMU_TRANSLATE_READ( R_EAX );
1.621 @@ -1114,6 +1200,7 @@
1.622 sh4_x86.tstate = TSTATE_NONE;
1.623 :}
1.624 MOV.L Rm, @Rn {:
1.625 + COUNT_INST(I_MOVL);
1.626 load_reg( R_EAX, Rn );
1.627 check_walign32(R_EAX);
1.628 MMU_TRANSLATE_WRITE( R_EAX );
1.629 @@ -1122,6 +1209,7 @@
1.630 sh4_x86.tstate = TSTATE_NONE;
1.631 :}
1.632 MOV.L Rm, @-Rn {:
1.633 + COUNT_INST(I_MOVL);
1.634 load_reg( R_EAX, Rn );
1.635 ADD_imm8s_r32( -4, R_EAX );
1.636 check_walign32( R_EAX );
1.637 @@ -1132,6 +1220,7 @@
1.638 sh4_x86.tstate = TSTATE_NONE;
1.639 :}
1.640 MOV.L Rm, @(R0, Rn) {:
1.641 + COUNT_INST(I_MOVL);
1.642 load_reg( R_EAX, 0 );
1.643 load_reg( R_ECX, Rn );
1.644 ADD_r32_r32( R_ECX, R_EAX );
1.645 @@ -1142,6 +1231,7 @@
1.646 sh4_x86.tstate = TSTATE_NONE;
1.647 :}
1.648 MOV.L R0, @(disp, GBR) {:
1.649 + COUNT_INST(I_MOVL);
1.650 load_spreg( R_EAX, R_GBR );
1.651 ADD_imm32_r32( disp, R_EAX );
1.652 check_walign32( R_EAX );
1.653 @@ -1151,6 +1241,7 @@
1.654 sh4_x86.tstate = TSTATE_NONE;
1.655 :}
1.656 MOV.L Rm, @(disp, Rn) {:
1.657 + COUNT_INST(I_MOVL);
1.658 load_reg( R_EAX, Rn );
1.659 ADD_imm32_r32( disp, R_EAX );
1.660 check_walign32( R_EAX );
1.661 @@ -1160,6 +1251,7 @@
1.662 sh4_x86.tstate = TSTATE_NONE;
1.663 :}
1.664 MOV.L @Rm, Rn {:
1.665 + COUNT_INST(I_MOVL);
1.666 load_reg( R_EAX, Rm );
1.667 check_ralign32( R_EAX );
1.668 MMU_TRANSLATE_READ( R_EAX );
1.669 @@ -1168,6 +1260,7 @@
1.670 sh4_x86.tstate = TSTATE_NONE;
1.671 :}
1.672 MOV.L @Rm+, Rn {:
1.673 + COUNT_INST(I_MOVL);
1.674 load_reg( R_EAX, Rm );
1.675 check_ralign32( R_EAX );
1.676 MMU_TRANSLATE_READ( R_EAX );
1.677 @@ -1177,6 +1270,7 @@
1.678 sh4_x86.tstate = TSTATE_NONE;
1.679 :}
1.680 MOV.L @(R0, Rm), Rn {:
1.681 + COUNT_INST(I_MOVL);
1.682 load_reg( R_EAX, 0 );
1.683 load_reg( R_ECX, Rm );
1.684 ADD_r32_r32( R_ECX, R_EAX );
1.685 @@ -1187,6 +1281,7 @@
1.686 sh4_x86.tstate = TSTATE_NONE;
1.687 :}
1.688 MOV.L @(disp, GBR), R0 {:
1.689 + COUNT_INST(I_MOVL);
1.690 load_spreg( R_EAX, R_GBR );
1.691 ADD_imm32_r32( disp, R_EAX );
1.692 check_ralign32( R_EAX );
1.693 @@ -1196,6 +1291,7 @@
1.694 sh4_x86.tstate = TSTATE_NONE;
1.695 :}
1.696 MOV.L @(disp, PC), Rn {:
1.697 + COUNT_INST(I_MOVLPC);
1.698 if( sh4_x86.in_delay_slot ) {
1.699 SLOTILLEGAL();
1.700 } else {
1.701 @@ -1226,6 +1322,7 @@
1.702 }
1.703 :}
1.704 MOV.L @(disp, Rm), Rn {:
1.705 + COUNT_INST(I_MOVL);
1.706 load_reg( R_EAX, Rm );
1.707 ADD_imm8s_r32( disp, R_EAX );
1.708 check_ralign32( R_EAX );
1.709 @@ -1235,6 +1332,7 @@
1.710 sh4_x86.tstate = TSTATE_NONE;
1.711 :}
1.712 MOV.W Rm, @Rn {:
1.713 + COUNT_INST(I_MOVW);
1.714 load_reg( R_EAX, Rn );
1.715 check_walign16( R_EAX );
1.716 MMU_TRANSLATE_WRITE( R_EAX )
1.717 @@ -1243,6 +1341,7 @@
1.718 sh4_x86.tstate = TSTATE_NONE;
1.719 :}
1.720 MOV.W Rm, @-Rn {:
1.721 + COUNT_INST(I_MOVW);
1.722 load_reg( R_EAX, Rn );
1.723 ADD_imm8s_r32( -2, R_EAX );
1.724 check_walign16( R_EAX );
1.725 @@ -1253,6 +1352,7 @@
1.726 sh4_x86.tstate = TSTATE_NONE;
1.727 :}
1.728 MOV.W Rm, @(R0, Rn) {:
1.729 + COUNT_INST(I_MOVW);
1.730 load_reg( R_EAX, 0 );
1.731 load_reg( R_ECX, Rn );
1.732 ADD_r32_r32( R_ECX, R_EAX );
1.733 @@ -1263,6 +1363,7 @@
1.734 sh4_x86.tstate = TSTATE_NONE;
1.735 :}
1.736 MOV.W R0, @(disp, GBR) {:
1.737 + COUNT_INST(I_MOVW);
1.738 load_spreg( R_EAX, R_GBR );
1.739 ADD_imm32_r32( disp, R_EAX );
1.740 check_walign16( R_EAX );
1.741 @@ -1272,6 +1373,7 @@
1.742 sh4_x86.tstate = TSTATE_NONE;
1.743 :}
1.744 MOV.W R0, @(disp, Rn) {:
1.745 + COUNT_INST(I_MOVW);
1.746 load_reg( R_EAX, Rn );
1.747 ADD_imm32_r32( disp, R_EAX );
1.748 check_walign16( R_EAX );
1.749 @@ -1281,6 +1383,7 @@
1.750 sh4_x86.tstate = TSTATE_NONE;
1.751 :}
1.752 MOV.W @Rm, Rn {:
1.753 + COUNT_INST(I_MOVW);
1.754 load_reg( R_EAX, Rm );
1.755 check_ralign16( R_EAX );
1.756 MMU_TRANSLATE_READ( R_EAX );
1.757 @@ -1289,6 +1392,7 @@
1.758 sh4_x86.tstate = TSTATE_NONE;
1.759 :}
1.760 MOV.W @Rm+, Rn {:
1.761 + COUNT_INST(I_MOVW);
1.762 load_reg( R_EAX, Rm );
1.763 check_ralign16( R_EAX );
1.764 MMU_TRANSLATE_READ( R_EAX );
1.765 @@ -1298,6 +1402,7 @@
1.766 sh4_x86.tstate = TSTATE_NONE;
1.767 :}
1.768 MOV.W @(R0, Rm), Rn {:
1.769 + COUNT_INST(I_MOVW);
1.770 load_reg( R_EAX, 0 );
1.771 load_reg( R_ECX, Rm );
1.772 ADD_r32_r32( R_ECX, R_EAX );
1.773 @@ -1308,6 +1413,7 @@
1.774 sh4_x86.tstate = TSTATE_NONE;
1.775 :}
1.776 MOV.W @(disp, GBR), R0 {:
1.777 + COUNT_INST(I_MOVW);
1.778 load_spreg( R_EAX, R_GBR );
1.779 ADD_imm32_r32( disp, R_EAX );
1.780 check_ralign16( R_EAX );
1.781 @@ -1317,6 +1423,7 @@
1.782 sh4_x86.tstate = TSTATE_NONE;
1.783 :}
1.784 MOV.W @(disp, PC), Rn {:
1.785 + COUNT_INST(I_MOVW);
1.786 if( sh4_x86.in_delay_slot ) {
1.787 SLOTILLEGAL();
1.788 } else {
1.789 @@ -1337,6 +1444,7 @@
1.790 }
1.791 :}
1.792 MOV.W @(disp, Rm), R0 {:
1.793 + COUNT_INST(I_MOVW);
1.794 load_reg( R_EAX, Rm );
1.795 ADD_imm32_r32( disp, R_EAX );
1.796 check_ralign16( R_EAX );
1.797 @@ -1346,6 +1454,7 @@
1.798 sh4_x86.tstate = TSTATE_NONE;
1.799 :}
1.800 MOVA @(disp, PC), R0 {:
1.801 + COUNT_INST(I_MOVA);
1.802 if( sh4_x86.in_delay_slot ) {
1.803 SLOTILLEGAL();
1.804 } else {
1.805 @@ -1356,6 +1465,7 @@
1.806 }
1.807 :}
1.808 MOVCA.L R0, @Rn {:
1.809 + COUNT_INST(I_MOVCA);
1.810 load_reg( R_EAX, Rn );
1.811 check_walign32( R_EAX );
1.812 MMU_TRANSLATE_WRITE( R_EAX );
1.813 @@ -1366,6 +1476,7 @@
1.814
1.815 /* Control transfer instructions */
1.816 BF disp {:
1.817 + COUNT_INST(I_BF);
1.818 if( sh4_x86.in_delay_slot ) {
1.819 SLOTILLEGAL();
1.820 } else {
1.821 @@ -1377,6 +1488,7 @@
1.822 }
1.823 :}
1.824 BF/S disp {:
1.825 + COUNT_INST(I_BFS);
1.826 if( sh4_x86.in_delay_slot ) {
1.827 SLOTILLEGAL();
1.828 } else {
1.829 @@ -1409,6 +1521,7 @@
1.830 }
1.831 :}
1.832 BRA disp {:
1.833 + COUNT_INST(I_BRA);
1.834 if( sh4_x86.in_delay_slot ) {
1.835 SLOTILLEGAL();
1.836 } else {
1.837 @@ -1428,6 +1541,7 @@
1.838 }
1.839 :}
1.840 BRAF Rn {:
1.841 + COUNT_INST(I_BRAF);
1.842 if( sh4_x86.in_delay_slot ) {
1.843 SLOTILLEGAL();
1.844 } else {
1.845 @@ -1449,6 +1563,7 @@
1.846 }
1.847 :}
1.848 BSR disp {:
1.849 + COUNT_INST(I_BSR);
1.850 if( sh4_x86.in_delay_slot ) {
1.851 SLOTILLEGAL();
1.852 } else {
1.853 @@ -1471,6 +1586,7 @@
1.854 }
1.855 :}
1.856 BSRF Rn {:
1.857 + COUNT_INST(I_BSRF);
1.858 if( sh4_x86.in_delay_slot ) {
1.859 SLOTILLEGAL();
1.860 } else {
1.861 @@ -1494,6 +1610,7 @@
1.862 }
1.863 :}
1.864 BT disp {:
1.865 + COUNT_INST(I_BT);
1.866 if( sh4_x86.in_delay_slot ) {
1.867 SLOTILLEGAL();
1.868 } else {
1.869 @@ -1505,6 +1622,7 @@
1.870 }
1.871 :}
1.872 BT/S disp {:
1.873 + COUNT_INST(I_BTS);
1.874 if( sh4_x86.in_delay_slot ) {
1.875 SLOTILLEGAL();
1.876 } else {
1.877 @@ -1535,6 +1653,7 @@
1.878 }
1.879 :}
1.880 JMP @Rn {:
1.881 + COUNT_INST(I_JMP);
1.882 if( sh4_x86.in_delay_slot ) {
1.883 SLOTILLEGAL();
1.884 } else {
1.885 @@ -1553,6 +1672,7 @@
1.886 }
1.887 :}
1.888 JSR @Rn {:
1.889 + COUNT_INST(I_JSR);
1.890 if( sh4_x86.in_delay_slot ) {
1.891 SLOTILLEGAL();
1.892 } else {
1.893 @@ -1575,6 +1695,7 @@
1.894 }
1.895 :}
1.896 RTE {:
1.897 + COUNT_INST(I_RTE);
1.898 if( sh4_x86.in_delay_slot ) {
1.899 SLOTILLEGAL();
1.900 } else {
1.901 @@ -1599,6 +1720,7 @@
1.902 }
1.903 :}
1.904 RTS {:
1.905 + COUNT_INST(I_RTS);
1.906 if( sh4_x86.in_delay_slot ) {
1.907 SLOTILLEGAL();
1.908 } else {
1.909 @@ -1617,6 +1739,7 @@
1.910 }
1.911 :}
1.912 TRAPA #imm {:
1.913 + COUNT_INST(I_TRAPA);
1.914 if( sh4_x86.in_delay_slot ) {
1.915 SLOTILLEGAL();
1.916 } else {
1.917 @@ -1631,6 +1754,7 @@
1.918 }
1.919 :}
1.920 UNDEF {:
1.921 + COUNT_INST(I_UNDEF);
1.922 if( sh4_x86.in_delay_slot ) {
1.923 SLOTILLEGAL();
1.924 } else {
1.925 @@ -1640,27 +1764,32 @@
1.926 :}
1.927
1.928 CLRMAC {:
1.929 + COUNT_INST(I_CLRMAC);
1.930 XOR_r32_r32(R_EAX, R_EAX);
1.931 store_spreg( R_EAX, R_MACL );
1.932 store_spreg( R_EAX, R_MACH );
1.933 sh4_x86.tstate = TSTATE_NONE;
1.934 :}
1.935 CLRS {:
1.936 + COUNT_INST(I_CLRS);
1.937 CLC();
1.938 SETC_sh4r(R_S);
1.939 sh4_x86.tstate = TSTATE_C;
1.940 :}
1.941 CLRT {:
1.942 + COUNT_INST(I_CLRT);
1.943 CLC();
1.944 SETC_t();
1.945 sh4_x86.tstate = TSTATE_C;
1.946 :}
1.947 SETS {:
1.948 + COUNT_INST(I_SETS);
1.949 STC();
1.950 SETC_sh4r(R_S);
1.951 sh4_x86.tstate = TSTATE_C;
1.952 :}
1.953 SETT {:
1.954 + COUNT_INST(I_SETT);
1.955 STC();
1.956 SETC_t();
1.957 sh4_x86.tstate = TSTATE_C;
1.958 @@ -1668,6 +1797,7 @@
1.959
1.960 /* Floating point moves */
1.961 FMOV FRm, FRn {:
1.962 + COUNT_INST(I_FMOV1);
1.963 /* As horrible as this looks, it's actually covering 5 separate cases:
1.964 * 1. 32-bit fr-to-fr (PR=0)
1.965 * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
1.966 @@ -1691,6 +1821,7 @@
1.967 sh4_x86.tstate = TSTATE_NONE;
1.968 :}
1.969 FMOV FRm, @Rn {:
1.970 + COUNT_INST(I_FMOV2);
1.971 check_fpuen();
1.972 load_reg( R_EAX, Rn );
1.973 check_walign32( R_EAX );
1.974 @@ -1711,6 +1842,7 @@
1.975 sh4_x86.tstate = TSTATE_NONE;
1.976 :}
1.977 FMOV @Rm, FRn {:
1.978 + COUNT_INST(I_FMOV5);
1.979 check_fpuen();
1.980 load_reg( R_EAX, Rm );
1.981 check_ralign32( R_EAX );
1.982 @@ -1731,6 +1863,7 @@
1.983 sh4_x86.tstate = TSTATE_NONE;
1.984 :}
1.985 FMOV FRm, @-Rn {:
1.986 + COUNT_INST(I_FMOV3);
1.987 check_fpuen();
1.988 load_reg( R_EAX, Rn );
1.989 check_walign32( R_EAX );
1.990 @@ -1757,6 +1890,7 @@
1.991 sh4_x86.tstate = TSTATE_NONE;
1.992 :}
1.993 FMOV @Rm+, FRn {:
1.994 + COUNT_INST(I_FMOV6);
1.995 check_fpuen();
1.996 load_reg( R_EAX, Rm );
1.997 check_ralign32( R_EAX );
1.998 @@ -1780,6 +1914,7 @@
1.999 sh4_x86.tstate = TSTATE_NONE;
1.1000 :}
1.1001 FMOV FRm, @(R0, Rn) {:
1.1002 + COUNT_INST(I_FMOV4);
1.1003 check_fpuen();
1.1004 load_reg( R_EAX, Rn );
1.1005 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
1.1006 @@ -1802,6 +1937,7 @@
1.1007 sh4_x86.tstate = TSTATE_NONE;
1.1008 :}
1.1009 FMOV @(R0, Rm), FRn {:
1.1010 + COUNT_INST(I_FMOV7);
1.1011 check_fpuen();
1.1012 load_reg( R_EAX, Rm );
1.1013 ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
1.1014 @@ -1824,6 +1960,7 @@
1.1015 sh4_x86.tstate = TSTATE_NONE;
1.1016 :}
1.1017 FLDI0 FRn {: /* IFF PR=0 */
1.1018 + COUNT_INST(I_FLDI0);
1.1019 check_fpuen();
1.1020 load_spreg( R_ECX, R_FPSCR );
1.1021 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1022 @@ -1834,6 +1971,7 @@
1.1023 sh4_x86.tstate = TSTATE_NONE;
1.1024 :}
1.1025 FLDI1 FRn {: /* IFF PR=0 */
1.1026 + COUNT_INST(I_FLDI1);
1.1027 check_fpuen();
1.1028 load_spreg( R_ECX, R_FPSCR );
1.1029 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1030 @@ -1845,6 +1983,7 @@
1.1031 :}
1.1032
1.1033 FLOAT FPUL, FRn {:
1.1034 + COUNT_INST(I_FLOAT);
1.1035 check_fpuen();
1.1036 load_spreg( R_ECX, R_FPSCR );
1.1037 FILD_sh4r(R_FPUL);
1.1038 @@ -1858,6 +1997,7 @@
1.1039 sh4_x86.tstate = TSTATE_NONE;
1.1040 :}
1.1041 FTRC FRm, FPUL {:
1.1042 + COUNT_INST(I_FTRC);
1.1043 check_fpuen();
1.1044 load_spreg( R_ECX, R_FPSCR );
1.1045 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1046 @@ -1892,18 +2032,21 @@
1.1047 sh4_x86.tstate = TSTATE_NONE;
1.1048 :}
1.1049 FLDS FRm, FPUL {:
1.1050 + COUNT_INST(I_FLDS);
1.1051 check_fpuen();
1.1052 load_fr( R_EAX, FRm );
1.1053 store_spreg( R_EAX, R_FPUL );
1.1054 sh4_x86.tstate = TSTATE_NONE;
1.1055 :}
1.1056 FSTS FPUL, FRn {:
1.1057 + COUNT_INST(I_FSTS);
1.1058 check_fpuen();
1.1059 load_spreg( R_EAX, R_FPUL );
1.1060 store_fr( R_EAX, FRn );
1.1061 sh4_x86.tstate = TSTATE_NONE;
1.1062 :}
1.1063 FCNVDS FRm, FPUL {:
1.1064 + COUNT_INST(I_FCNVDS);
1.1065 check_fpuen();
1.1066 load_spreg( R_ECX, R_FPSCR );
1.1067 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1068 @@ -1914,6 +2057,7 @@
1.1069 sh4_x86.tstate = TSTATE_NONE;
1.1070 :}
1.1071 FCNVSD FPUL, FRn {:
1.1072 + COUNT_INST(I_FCNVSD);
1.1073 check_fpuen();
1.1074 load_spreg( R_ECX, R_FPSCR );
1.1075 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1076 @@ -1926,6 +2070,7 @@
1.1077
1.1078 /* Floating point instructions */
1.1079 FABS FRn {:
1.1080 + COUNT_INST(I_FABS);
1.1081 check_fpuen();
1.1082 load_spreg( R_ECX, R_FPSCR );
1.1083 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1084 @@ -1942,6 +2087,7 @@
1.1085 sh4_x86.tstate = TSTATE_NONE;
1.1086 :}
1.1087 FADD FRm, FRn {:
1.1088 + COUNT_INST(I_FADD);
1.1089 check_fpuen();
1.1090 load_spreg( R_ECX, R_FPSCR );
1.1091 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1092 @@ -1960,6 +2106,7 @@
1.1093 sh4_x86.tstate = TSTATE_NONE;
1.1094 :}
1.1095 FDIV FRm, FRn {:
1.1096 + COUNT_INST(I_FDIV);
1.1097 check_fpuen();
1.1098 load_spreg( R_ECX, R_FPSCR );
1.1099 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1100 @@ -1978,6 +2125,7 @@
1.1101 sh4_x86.tstate = TSTATE_NONE;
1.1102 :}
1.1103 FMAC FR0, FRm, FRn {:
1.1104 + COUNT_INST(I_FMAC);
1.1105 check_fpuen();
1.1106 load_spreg( R_ECX, R_FPSCR );
1.1107 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1108 @@ -2001,6 +2149,7 @@
1.1109 :}
1.1110
1.1111 FMUL FRm, FRn {:
1.1112 + COUNT_INST(I_FMUL);
1.1113 check_fpuen();
1.1114 load_spreg( R_ECX, R_FPSCR );
1.1115 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1116 @@ -2019,6 +2168,7 @@
1.1117 sh4_x86.tstate = TSTATE_NONE;
1.1118 :}
1.1119 FNEG FRn {:
1.1120 + COUNT_INST(I_FNEG);
1.1121 check_fpuen();
1.1122 load_spreg( R_ECX, R_FPSCR );
1.1123 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1124 @@ -2035,6 +2185,7 @@
1.1125 sh4_x86.tstate = TSTATE_NONE;
1.1126 :}
1.1127 FSRRA FRn {:
1.1128 + COUNT_INST(I_FSRRA);
1.1129 check_fpuen();
1.1130 load_spreg( R_ECX, R_FPSCR );
1.1131 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1132 @@ -2048,6 +2199,7 @@
1.1133 sh4_x86.tstate = TSTATE_NONE;
1.1134 :}
1.1135 FSQRT FRn {:
1.1136 + COUNT_INST(I_FSQRT);
1.1137 check_fpuen();
1.1138 load_spreg( R_ECX, R_FPSCR );
1.1139 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1140 @@ -2064,6 +2216,7 @@
1.1141 sh4_x86.tstate = TSTATE_NONE;
1.1142 :}
1.1143 FSUB FRm, FRn {:
1.1144 + COUNT_INST(I_FSUB);
1.1145 check_fpuen();
1.1146 load_spreg( R_ECX, R_FPSCR );
1.1147 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1148 @@ -2083,6 +2236,7 @@
1.1149 :}
1.1150
1.1151 FCMP/EQ FRm, FRn {:
1.1152 + COUNT_INST(I_FCMPEQ);
1.1153 check_fpuen();
1.1154 load_spreg( R_ECX, R_FPSCR );
1.1155 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1156 @@ -2100,6 +2254,7 @@
1.1157 sh4_x86.tstate = TSTATE_NONE;
1.1158 :}
1.1159 FCMP/GT FRm, FRn {:
1.1160 + COUNT_INST(I_FCMPGT);
1.1161 check_fpuen();
1.1162 load_spreg( R_ECX, R_FPSCR );
1.1163 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1164 @@ -2118,6 +2273,7 @@
1.1165 :}
1.1166
1.1167 FSCA FPUL, FRn {:
1.1168 + COUNT_INST(I_FSCA);
1.1169 check_fpuen();
1.1170 load_spreg( R_ECX, R_FPSCR );
1.1171 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1172 @@ -2129,6 +2285,7 @@
1.1173 sh4_x86.tstate = TSTATE_NONE;
1.1174 :}
1.1175 FIPR FVm, FVn {:
1.1176 + COUNT_INST(I_FIPR);
1.1177 check_fpuen();
1.1178 load_spreg( R_ECX, R_FPSCR );
1.1179 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1180 @@ -2154,6 +2311,7 @@
1.1181 sh4_x86.tstate = TSTATE_NONE;
1.1182 :}
1.1183 FTRV XMTRX, FVn {:
1.1184 + COUNT_INST(I_FTRV);
1.1185 check_fpuen();
1.1186 load_spreg( R_ECX, R_FPSCR );
1.1187 TEST_imm32_r32( FPSCR_PR, R_ECX );
1.1188 @@ -2165,6 +2323,7 @@
1.1189 :}
1.1190
1.1191 FRCHG {:
1.1192 + COUNT_INST(I_FRCHG);
1.1193 check_fpuen();
1.1194 load_spreg( R_ECX, R_FPSCR );
1.1195 XOR_imm32_r32( FPSCR_FR, R_ECX );
1.1196 @@ -2173,6 +2332,7 @@
1.1197 sh4_x86.tstate = TSTATE_NONE;
1.1198 :}
1.1199 FSCHG {:
1.1200 + COUNT_INST(I_FSCHG);
1.1201 check_fpuen();
1.1202 load_spreg( R_ECX, R_FPSCR );
1.1203 XOR_imm32_r32( FPSCR_SZ, R_ECX );
1.1204 @@ -2182,6 +2342,7 @@
1.1205
1.1206 /* Processor control instructions */
1.1207 LDC Rm, SR {:
1.1208 + COUNT_INST(I_LDCSR);
1.1209 if( sh4_x86.in_delay_slot ) {
1.1210 SLOTILLEGAL();
1.1211 } else {
1.1212 @@ -2194,46 +2355,54 @@
1.1213 }
1.1214 :}
1.1215 LDC Rm, GBR {:
1.1216 + COUNT_INST(I_LDC);
1.1217 load_reg( R_EAX, Rm );
1.1218 store_spreg( R_EAX, R_GBR );
1.1219 :}
1.1220 LDC Rm, VBR {:
1.1221 + COUNT_INST(I_LDC);
1.1222 check_priv();
1.1223 load_reg( R_EAX, Rm );
1.1224 store_spreg( R_EAX, R_VBR );
1.1225 sh4_x86.tstate = TSTATE_NONE;
1.1226 :}
1.1227 LDC Rm, SSR {:
1.1228 + COUNT_INST(I_LDC);
1.1229 check_priv();
1.1230 load_reg( R_EAX, Rm );
1.1231 store_spreg( R_EAX, R_SSR );
1.1232 sh4_x86.tstate = TSTATE_NONE;
1.1233 :}
1.1234 LDC Rm, SGR {:
1.1235 + COUNT_INST(I_LDC);
1.1236 check_priv();
1.1237 load_reg( R_EAX, Rm );
1.1238 store_spreg( R_EAX, R_SGR );
1.1239 sh4_x86.tstate = TSTATE_NONE;
1.1240 :}
1.1241 LDC Rm, SPC {:
1.1242 + COUNT_INST(I_LDC);
1.1243 check_priv();
1.1244 load_reg( R_EAX, Rm );
1.1245 store_spreg( R_EAX, R_SPC );
1.1246 sh4_x86.tstate = TSTATE_NONE;
1.1247 :}
1.1248 LDC Rm, DBR {:
1.1249 + COUNT_INST(I_LDC);
1.1250 check_priv();
1.1251 load_reg( R_EAX, Rm );
1.1252 store_spreg( R_EAX, R_DBR );
1.1253 sh4_x86.tstate = TSTATE_NONE;
1.1254 :}
1.1255 LDC Rm, Rn_BANK {:
1.1256 + COUNT_INST(I_LDC);
1.1257 check_priv();
1.1258 load_reg( R_EAX, Rm );
1.1259 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
1.1260 sh4_x86.tstate = TSTATE_NONE;
1.1261 :}
1.1262 LDC.L @Rm+, GBR {:
1.1263 + COUNT_INST(I_LDCM);
1.1264 load_reg( R_EAX, Rm );
1.1265 check_ralign32( R_EAX );
1.1266 MMU_TRANSLATE_READ( R_EAX );
1.1267 @@ -2243,6 +2412,7 @@
1.1268 sh4_x86.tstate = TSTATE_NONE;
1.1269 :}
1.1270 LDC.L @Rm+, SR {:
1.1271 + COUNT_INST(I_LDCSRM);
1.1272 if( sh4_x86.in_delay_slot ) {
1.1273 SLOTILLEGAL();
1.1274 } else {
1.1275 @@ -2259,6 +2429,7 @@
1.1276 }
1.1277 :}
1.1278 LDC.L @Rm+, VBR {:
1.1279 + COUNT_INST(I_LDCM);
1.1280 check_priv();
1.1281 load_reg( R_EAX, Rm );
1.1282 check_ralign32( R_EAX );
1.1283 @@ -2269,6 +2440,7 @@
1.1284 sh4_x86.tstate = TSTATE_NONE;
1.1285 :}
1.1286 LDC.L @Rm+, SSR {:
1.1287 + COUNT_INST(I_LDCM);
1.1288 check_priv();
1.1289 load_reg( R_EAX, Rm );
1.1290 check_ralign32( R_EAX );
1.1291 @@ -2279,6 +2451,7 @@
1.1292 sh4_x86.tstate = TSTATE_NONE;
1.1293 :}
1.1294 LDC.L @Rm+, SGR {:
1.1295 + COUNT_INST(I_LDCM);
1.1296 check_priv();
1.1297 load_reg( R_EAX, Rm );
1.1298 check_ralign32( R_EAX );
1.1299 @@ -2289,6 +2462,7 @@
1.1300 sh4_x86.tstate = TSTATE_NONE;
1.1301 :}
1.1302 LDC.L @Rm+, SPC {:
1.1303 + COUNT_INST(I_LDCM);
1.1304 check_priv();
1.1305 load_reg( R_EAX, Rm );
1.1306 check_ralign32( R_EAX );
1.1307 @@ -2299,6 +2473,7 @@
1.1308 sh4_x86.tstate = TSTATE_NONE;
1.1309 :}
1.1310 LDC.L @Rm+, DBR {:
1.1311 + COUNT_INST(I_LDCM);
1.1312 check_priv();
1.1313 load_reg( R_EAX, Rm );
1.1314 check_ralign32( R_EAX );
1.1315 @@ -2309,6 +2484,7 @@
1.1316 sh4_x86.tstate = TSTATE_NONE;
1.1317 :}
1.1318 LDC.L @Rm+, Rn_BANK {:
1.1319 + COUNT_INST(I_LDCM);
1.1320 check_priv();
1.1321 load_reg( R_EAX, Rm );
1.1322 check_ralign32( R_EAX );
1.1323 @@ -2319,12 +2495,14 @@
1.1324 sh4_x86.tstate = TSTATE_NONE;
1.1325 :}
1.1326 LDS Rm, FPSCR {:
1.1327 + COUNT_INST(I_LDS);
1.1328 check_fpuen();
1.1329 load_reg( R_EAX, Rm );
1.1330 call_func1( sh4_write_fpscr, R_EAX );
1.1331 sh4_x86.tstate = TSTATE_NONE;
1.1332 :}
1.1333 LDS.L @Rm+, FPSCR {:
1.1334 + COUNT_INST(I_LDS);
1.1335 check_fpuen();
1.1336 load_reg( R_EAX, Rm );
1.1337 check_ralign32( R_EAX );
1.1338 @@ -2335,11 +2513,13 @@
1.1339 sh4_x86.tstate = TSTATE_NONE;
1.1340 :}
1.1341 LDS Rm, FPUL {:
1.1342 + COUNT_INST(I_LDS);
1.1343 check_fpuen();
1.1344 load_reg( R_EAX, Rm );
1.1345 store_spreg( R_EAX, R_FPUL );
1.1346 :}
1.1347 LDS.L @Rm+, FPUL {:
1.1348 + COUNT_INST(I_LDSM);
1.1349 check_fpuen();
1.1350 load_reg( R_EAX, Rm );
1.1351 check_ralign32( R_EAX );
1.1352 @@ -2350,10 +2530,12 @@
1.1353 sh4_x86.tstate = TSTATE_NONE;
1.1354 :}
1.1355 LDS Rm, MACH {:
1.1356 + COUNT_INST(I_LDS);
1.1357 load_reg( R_EAX, Rm );
1.1358 store_spreg( R_EAX, R_MACH );
1.1359 :}
1.1360 LDS.L @Rm+, MACH {:
1.1361 + COUNT_INST(I_LDSM);
1.1362 load_reg( R_EAX, Rm );
1.1363 check_ralign32( R_EAX );
1.1364 MMU_TRANSLATE_READ( R_EAX );
1.1365 @@ -2363,10 +2545,12 @@
1.1366 sh4_x86.tstate = TSTATE_NONE;
1.1367 :}
1.1368 LDS Rm, MACL {:
1.1369 + COUNT_INST(I_LDS);
1.1370 load_reg( R_EAX, Rm );
1.1371 store_spreg( R_EAX, R_MACL );
1.1372 :}
1.1373 LDS.L @Rm+, MACL {:
1.1374 + COUNT_INST(I_LDSM);
1.1375 load_reg( R_EAX, Rm );
1.1376 check_ralign32( R_EAX );
1.1377 MMU_TRANSLATE_READ( R_EAX );
1.1378 @@ -2376,10 +2560,12 @@
1.1379 sh4_x86.tstate = TSTATE_NONE;
1.1380 :}
1.1381 LDS Rm, PR {:
1.1382 + COUNT_INST(I_LDS);
1.1383 load_reg( R_EAX, Rm );
1.1384 store_spreg( R_EAX, R_PR );
1.1385 :}
1.1386 LDS.L @Rm+, PR {:
1.1387 + COUNT_INST(I_LDSM);
1.1388 load_reg( R_EAX, Rm );
1.1389 check_ralign32( R_EAX );
1.1390 MMU_TRANSLATE_READ( R_EAX );
1.1391 @@ -2389,12 +2575,20 @@
1.1392 sh4_x86.tstate = TSTATE_NONE;
1.1393 :}
1.1394 LDTLB {:
1.1395 + COUNT_INST(I_LDTLB);
1.1396 call_func0( MMU_ldtlb );
1.1397 :}
1.1398 -OCBI @Rn {: :}
1.1399 -OCBP @Rn {: :}
1.1400 -OCBWB @Rn {: :}
1.1401 +OCBI @Rn {:
1.1402 + COUNT_INST(I_OCBI);
1.1403 +:}
1.1404 +OCBP @Rn {:
1.1405 + COUNT_INST(I_OCBP);
1.1406 +:}
1.1407 +OCBWB @Rn {:
1.1408 + COUNT_INST(I_OCBWB);
1.1409 +:}
1.1410 PREF @Rn {:
1.1411 + COUNT_INST(I_PREF);
1.1412 load_reg( R_EAX, Rn );
1.1413 MOV_r32_r32( R_EAX, R_ECX );
1.1414 AND_imm32_r32( 0xFC000000, R_EAX );
1.1415 @@ -2407,6 +2601,7 @@
1.1416 sh4_x86.tstate = TSTATE_NONE;
1.1417 :}
1.1418 SLEEP {:
1.1419 + COUNT_INST(I_SLEEP);
1.1420 check_priv();
1.1421 call_func0( sh4_sleep );
1.1422 sh4_x86.tstate = TSTATE_NONE;
1.1423 @@ -2414,52 +2609,61 @@
1.1424 return 2;
1.1425 :}
1.1426 STC SR, Rn {:
1.1427 + COUNT_INST(I_STCSR);
1.1428 check_priv();
1.1429 call_func0(sh4_read_sr);
1.1430 store_reg( R_EAX, Rn );
1.1431 sh4_x86.tstate = TSTATE_NONE;
1.1432 :}
1.1433 STC GBR, Rn {:
1.1434 + COUNT_INST(I_STC);
1.1435 load_spreg( R_EAX, R_GBR );
1.1436 store_reg( R_EAX, Rn );
1.1437 :}
1.1438 STC VBR, Rn {:
1.1439 + COUNT_INST(I_STC);
1.1440 check_priv();
1.1441 load_spreg( R_EAX, R_VBR );
1.1442 store_reg( R_EAX, Rn );
1.1443 sh4_x86.tstate = TSTATE_NONE;
1.1444 :}
1.1445 STC SSR, Rn {:
1.1446 + COUNT_INST(I_STC);
1.1447 check_priv();
1.1448 load_spreg( R_EAX, R_SSR );
1.1449 store_reg( R_EAX, Rn );
1.1450 sh4_x86.tstate = TSTATE_NONE;
1.1451 :}
1.1452 STC SPC, Rn {:
1.1453 + COUNT_INST(I_STC);
1.1454 check_priv();
1.1455 load_spreg( R_EAX, R_SPC );
1.1456 store_reg( R_EAX, Rn );
1.1457 sh4_x86.tstate = TSTATE_NONE;
1.1458 :}
1.1459 STC SGR, Rn {:
1.1460 + COUNT_INST(I_STC);
1.1461 check_priv();
1.1462 load_spreg( R_EAX, R_SGR );
1.1463 store_reg( R_EAX, Rn );
1.1464 sh4_x86.tstate = TSTATE_NONE;
1.1465 :}
1.1466 STC DBR, Rn {:
1.1467 + COUNT_INST(I_STC);
1.1468 check_priv();
1.1469 load_spreg( R_EAX, R_DBR );
1.1470 store_reg( R_EAX, Rn );
1.1471 sh4_x86.tstate = TSTATE_NONE;
1.1472 :}
1.1473 STC Rm_BANK, Rn {:
1.1474 + COUNT_INST(I_STC);
1.1475 check_priv();
1.1476 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
1.1477 store_reg( R_EAX, Rn );
1.1478 sh4_x86.tstate = TSTATE_NONE;
1.1479 :}
1.1480 STC.L SR, @-Rn {:
1.1481 + COUNT_INST(I_STCSRM);
1.1482 check_priv();
1.1483 load_reg( R_EAX, Rn );
1.1484 check_walign32( R_EAX );
1.1485 @@ -2473,6 +2677,7 @@
1.1486 sh4_x86.tstate = TSTATE_NONE;
1.1487 :}
1.1488 STC.L VBR, @-Rn {:
1.1489 + COUNT_INST(I_STCM);
1.1490 check_priv();
1.1491 load_reg( R_EAX, Rn );
1.1492 check_walign32( R_EAX );
1.1493 @@ -2484,6 +2689,7 @@
1.1494 sh4_x86.tstate = TSTATE_NONE;
1.1495 :}
1.1496 STC.L SSR, @-Rn {:
1.1497 + COUNT_INST(I_STCM);
1.1498 check_priv();
1.1499 load_reg( R_EAX, Rn );
1.1500 check_walign32( R_EAX );
1.1501 @@ -2495,6 +2701,7 @@
1.1502 sh4_x86.tstate = TSTATE_NONE;
1.1503 :}
1.1504 STC.L SPC, @-Rn {:
1.1505 + COUNT_INST(I_STCM);
1.1506 check_priv();
1.1507 load_reg( R_EAX, Rn );
1.1508 check_walign32( R_EAX );
1.1509 @@ -2506,6 +2713,7 @@
1.1510 sh4_x86.tstate = TSTATE_NONE;
1.1511 :}
1.1512 STC.L SGR, @-Rn {:
1.1513 + COUNT_INST(I_STCM);
1.1514 check_priv();
1.1515 load_reg( R_EAX, Rn );
1.1516 check_walign32( R_EAX );
1.1517 @@ -2517,6 +2725,7 @@
1.1518 sh4_x86.tstate = TSTATE_NONE;
1.1519 :}
1.1520 STC.L DBR, @-Rn {:
1.1521 + COUNT_INST(I_STCM);
1.1522 check_priv();
1.1523 load_reg( R_EAX, Rn );
1.1524 check_walign32( R_EAX );
1.1525 @@ -2528,6 +2737,7 @@
1.1526 sh4_x86.tstate = TSTATE_NONE;
1.1527 :}
1.1528 STC.L Rm_BANK, @-Rn {:
1.1529 + COUNT_INST(I_STCM);
1.1530 check_priv();
1.1531 load_reg( R_EAX, Rn );
1.1532 check_walign32( R_EAX );
1.1533 @@ -2539,6 +2749,7 @@
1.1534 sh4_x86.tstate = TSTATE_NONE;
1.1535 :}
1.1536 STC.L GBR, @-Rn {:
1.1537 + COUNT_INST(I_STCM);
1.1538 load_reg( R_EAX, Rn );
1.1539 check_walign32( R_EAX );
1.1540 ADD_imm8s_r32( -4, R_EAX );
1.1541 @@ -2549,11 +2760,13 @@
1.1542 sh4_x86.tstate = TSTATE_NONE;
1.1543 :}
1.1544 STS FPSCR, Rn {:
1.1545 + COUNT_INST(I_STS);
1.1546 check_fpuen();
1.1547 load_spreg( R_EAX, R_FPSCR );
1.1548 store_reg( R_EAX, Rn );
1.1549 :}
1.1550 STS.L FPSCR, @-Rn {:
1.1551 + COUNT_INST(I_STSM);
1.1552 check_fpuen();
1.1553 load_reg( R_EAX, Rn );
1.1554 check_walign32( R_EAX );
1.1555 @@ -2565,11 +2778,13 @@
1.1556 sh4_x86.tstate = TSTATE_NONE;
1.1557 :}
1.1558 STS FPUL, Rn {:
1.1559 + COUNT_INST(I_STS);
1.1560 check_fpuen();
1.1561 load_spreg( R_EAX, R_FPUL );
1.1562 store_reg( R_EAX, Rn );
1.1563 :}
1.1564 STS.L FPUL, @-Rn {:
1.1565 + COUNT_INST(I_STSM);
1.1566 check_fpuen();
1.1567 load_reg( R_EAX, Rn );
1.1568 check_walign32( R_EAX );
1.1569 @@ -2581,10 +2796,12 @@
1.1570 sh4_x86.tstate = TSTATE_NONE;
1.1571 :}
1.1572 STS MACH, Rn {:
1.1573 + COUNT_INST(I_STS);
1.1574 load_spreg( R_EAX, R_MACH );
1.1575 store_reg( R_EAX, Rn );
1.1576 :}
1.1577 STS.L MACH, @-Rn {:
1.1578 + COUNT_INST(I_STSM);
1.1579 load_reg( R_EAX, Rn );
1.1580 check_walign32( R_EAX );
1.1581 ADD_imm8s_r32( -4, R_EAX );
1.1582 @@ -2595,10 +2812,12 @@
1.1583 sh4_x86.tstate = TSTATE_NONE;
1.1584 :}
1.1585 STS MACL, Rn {:
1.1586 + COUNT_INST(I_STS);
1.1587 load_spreg( R_EAX, R_MACL );
1.1588 store_reg( R_EAX, Rn );
1.1589 :}
1.1590 STS.L MACL, @-Rn {:
1.1591 + COUNT_INST(I_STSM);
1.1592 load_reg( R_EAX, Rn );
1.1593 check_walign32( R_EAX );
1.1594 ADD_imm8s_r32( -4, R_EAX );
1.1595 @@ -2609,10 +2828,12 @@
1.1596 sh4_x86.tstate = TSTATE_NONE;
1.1597 :}
1.1598 STS PR, Rn {:
1.1599 + COUNT_INST(I_STS);
1.1600 load_spreg( R_EAX, R_PR );
1.1601 store_reg( R_EAX, Rn );
1.1602 :}
1.1603 STS.L PR, @-Rn {:
1.1604 + COUNT_INST(I_STSM);
1.1605 load_reg( R_EAX, Rn );
1.1606 check_walign32( R_EAX );
1.1607 ADD_imm8s_r32( -4, R_EAX );
1.1608 @@ -2623,7 +2844,10 @@
1.1609 sh4_x86.tstate = TSTATE_NONE;
1.1610 :}
1.1611
1.1612 -NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
1.1613 +NOP {:
1.1614 + COUNT_INST(I_NOP);
1.1615 + /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
1.1616 +:}
1.1617 %%
1.1618 sh4_x86.in_delay_slot = DELAY_NONE;
1.1619 return 0;
.