Search
lxdream.org :: lxdream/test/sh4/excslot.s :: diff
lxdream 0.9.1
released Jun 29
Download Now
filename test/sh4/excslot.s
changeset 231:a9e61a96a885
next233:f8333b94f503
author nkeynes
date Tue Sep 26 11:05:38 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add BT, BT/S, CMP/EQ, CMP/GE, CMP/GT, CMP/HI, CMP/HS tests
Add general slot-illegal exception test
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/test/sh4/excslot.s Tue Sep 26 11:05:38 2006 +0000
1.3 @@ -0,0 +1,189 @@
1.4 +.section .text
1.5 +.include "sh4/inc.s"
1.6 +!
1.7 +! Test for all cases that raise a slot-illegal exception (according to the SH4
1.8 +! manual). See Page 103 of the Hitachi manual
1.9 +
1.10 +.global _test_slot_illegal
1.11 +_test_slot_illegal:
1.12 + start_test
1.13 +
1.14 +! First the easy ones - instructions not permitted in delay slots at any
1.15 +! time:
1.16 +! JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA,
1.17 +! LDC (to SR), MOV pcrel, MOVA
1.18 +!
1.19 +! Note that the tests use BSR as the branch instruction, and assume it
1.20 +! functions correctly.
1.21 +
1.22 +test_slot_1: !JMP
1.23 + add #1, r12
1.24 + expect_exc 0x000001A0
1.25 +test_slot_1_pc:
1.26 + bsr test_slot_fail
1.27 + jmp @r3
1.28 + assert_exc_caught test_slot_str_k1 test_slot_1_pc
1.29 +
1.30 +test_slot_2: ! JSR
1.31 + add #1, r12
1.32 + expect_exc 0x000001A0
1.33 +test_slot_2_pc:
1.34 + bsr test_slot_fail
1.35 + jsr @r3
1.36 + assert_exc_caught test_slot_str_k1 test_slot_2_pc
1.37 + bra test_slot_3
1.38 + nop
1.39 +test_slot_str_k1:
1.40 + .long test_slot_str
1.41 +
1.42 +test_slot_3: ! BRA
1.43 + add #1, r12
1.44 + expect_exc 0x000001A0
1.45 +test_slot_3_pc:
1.46 + bsr test_slot_fail
1.47 + bra test_slot_fail
1.48 + assert_exc_caught test_slot_str_k test_slot_3_pc
1.49 +
1.50 +test_slot_4: ! BRAF
1.51 + add #1, r12
1.52 + expect_exc 0x000001A0
1.53 +test_slot_4_pc:
1.54 + bsr test_slot_fail
1.55 + braf r3
1.56 + assert_exc_caught test_slot_str_k test_slot_4_pc
1.57 +
1.58 +test_slot_5: ! BSR
1.59 + add #1, r12
1.60 + expect_exc 0x000001A0
1.61 +test_slot_5_pc:
1.62 + bsr test_slot_fail
1.63 + bsr test_slot_fail
1.64 + assert_exc_caught test_slot_str_k test_slot_5_pc
1.65 +
1.66 +test_slot_6: ! BSRF
1.67 + add #1, r12
1.68 + expect_exc 0x000001A0
1.69 +test_slot_6_pc:
1.70 + bsr test_slot_fail
1.71 + bsrf r3
1.72 + assert_exc_caught test_slot_str_k test_slot_6_pc
1.73 +
1.74 +test_slot_7: ! BF
1.75 + add #1, r12
1.76 + expect_exc 0x000001A0
1.77 +test_slot_7_pc:
1.78 + bsr test_slot_fail
1.79 + bf test_slot_7_fail
1.80 +test_slot_7_fail:
1.81 + assert_exc_caught test_slot_str_k test_slot_7_pc
1.82 +
1.83 +test_slot_8: ! BT
1.84 + add #1, r12
1.85 + expect_exc 0x000001A0
1.86 +test_slot_8_pc:
1.87 + bsr test_slot_fail
1.88 + bt test_slot_8_fail
1.89 +test_slot_8_fail:
1.90 + assert_exc_caught test_slot_str_k test_slot_8_pc
1.91 +
1.92 +test_slot_9: ! BF/S
1.93 + add #1, r12
1.94 + expect_exc 0x000001A0
1.95 +test_slot_9_pc:
1.96 + bsr test_slot_fail
1.97 + bf/s test_slot_9_fail
1.98 +test_slot_9_fail:
1.99 + assert_exc_caught test_slot_str_k test_slot_9_pc
1.100 +
1.101 +test_slot_10: ! BT/S
1.102 + add #1, r12
1.103 + expect_exc 0x000001A0
1.104 +test_slot_10_pc:
1.105 + bsr test_slot_fail
1.106 + bt/s test_slot_10_fail
1.107 +test_slot_10_fail:
1.108 + assert_exc_caught test_slot_str_k test_slot_10_pc
1.109 +
1.110 +test_slot_11: ! TRAPA
1.111 + add #1, r12
1.112 + expect_exc 0x000001A0
1.113 +test_slot_11_pc:
1.114 + bsr test_slot_fail
1.115 + trapa #12
1.116 + assert_exc_caught test_slot_str_k test_slot_11_pc
1.117 +
1.118 +test_slot_12: ! LDC r0, sr
1.119 + add #1, r12
1.120 + expect_exc 0x000001A0
1.121 + stc sr, r0
1.122 +test_slot_12_pc:
1.123 + bsr test_slot_fail
1.124 + ldc r0, sr
1.125 + assert_exc_caught test_slot_str_k test_slot_12_pc
1.126 +
1.127 +test_slot_13: ! LDC @r0, sr
1.128 + add #1, r12
1.129 + expect_exc 0x000001A0
1.130 + stc sr, r1
1.131 + mova test_slot_13_temp, r0
1.132 + mov.l r1, @r0
1.133 +test_slot_13_pc:
1.134 + bsr test_slot_fail
1.135 + ldc.l @r0+, sr
1.136 + assert_exc_caught test_slot_str_k test_slot_13_pc
1.137 + bra test_slot_14
1.138 + nop
1.139 +test_slot_13_temp:
1.140 + .long 0
1.141 +
1.142 +test_slot_14: ! MOVA
1.143 + add #1, r12
1.144 + expect_exc 0x000001A0
1.145 +test_slot_14_pc:
1.146 + bsr test_slot_fail
1.147 + mova test_slot_15, r0
1.148 + assert_exc_caught test_slot_str_k test_slot_14_pc
1.149 +
1.150 +test_slot_15: ! MOV.W pcrel, Rn
1.151 + add #1, r12
1.152 + expect_exc 0x000001A0
1.153 +test_slot_15_pc:
1.154 + bsr test_slot_fail
1.155 + mov.w test_slot_16, r0
1.156 + assert_exc_caught test_slot_str_k test_slot_15_pc
1.157 +
1.158 +test_slot_16: ! MOV.L pcrel, Rn
1.159 + add #1, r12
1.160 + expect_exc 0x000001A0
1.161 +test_slot_16_pc:
1.162 + bsr test_slot_fail
1.163 + mov.l test_slot_str_k, r0
1.164 + assert_exc_caught test_slot_str_k test_slot_16_pc
1.165 +
1.166 +test_slot_17: ! "Undefined" 0xFFFD
1.167 + add #1, r12
1.168 + expect_exc 0x000001A0
1.169 +test_slot_17_pc:
1.170 + bsr test_slot_fail
1.171 + .word 0xFFFD
1.172 + assert_exc_caught test_slot_str_k test_slot_17_pc
1.173 +
1.174 +!
1.175 +! Ok now the privilege tests. These should raise SLOT_ILLEGAL when executed
1.176 +! in a delay slot (otherwise it's GENERAL_ILLEGAL)
1.177 +! TODO: need mode-switch code
1.178 +
1.179 +test_slot_end:
1.180 + end_test test_slot_str_k
1.181 +
1.182 +! Returns after the delay slot, which should hit the "no exception" test
1.183 +test_slot_fail:
1.184 + rts
1.185 + nop
1.186 +
1.187 +test_slot_str_k:
1.188 + .long test_slot_str
1.189 +test_slot_str:
1.190 + .string "SLOT-ILLEGAL"
1.191 +
1.192 +
1.193 \ No newline at end of file
.