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lxdream.org :: lxdream/src/sh4/sh4x86.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 526:ba3da45b5754
prev502:c4ecae2b1b5e
next527:14c9489f647e
author nkeynes
date Sat Nov 17 06:04:19 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Don't build the translator if the architecture is unsupported. Also tidy things up a little to allow (theoretically) different translators to be selected at build time.
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.c Thu Nov 08 11:54:16 2007 +0000
1.2 +++ b/src/sh4/sh4x86.c Sat Nov 17 06:04:19 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4x86.c,v 1.19 2007-11-08 11:54:16 nkeynes Exp $
1.6 + * $Id: sh4x86.in,v 1.20 2007-11-08 11:54:16 nkeynes Exp $
1.7 *
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -522,7 +522,7 @@
1.11 * @return true if the instruction marks the end of a basic block
1.12 * (eg a branch or
1.13 */
1.14 -uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
1.15 +uint32_t sh4_translate_instruction( sh4addr_t pc )
1.16 {
1.17 uint32_t ir;
1.18 /* Read instruction */
1.19 @@ -623,7 +623,7 @@
1.20 store_spreg( R_ECX, REG_OFFSET(pc) );
1.21 sh4_x86.in_delay_slot = TRUE;
1.22 sh4_x86.tstate = TSTATE_NONE;
1.23 - sh4_x86_translate_instruction( pc + 2 );
1.24 + sh4_translate_instruction( pc + 2 );
1.25 exit_block_pcset(pc+2);
1.26 sh4_x86.branch_taken = TRUE;
1.27 return 4;
1.28 @@ -641,7 +641,7 @@
1.29 store_spreg( R_EAX, REG_OFFSET(pc) );
1.30 sh4_x86.in_delay_slot = TRUE;
1.31 sh4_x86.tstate = TSTATE_NONE;
1.32 - sh4_x86_translate_instruction( pc + 2 );
1.33 + sh4_translate_instruction( pc + 2 );
1.34 exit_block_pcset(pc+2);
1.35 sh4_x86.branch_taken = TRUE;
1.36 return 4;
1.37 @@ -885,7 +885,7 @@
1.38 load_spreg( R_ECX, R_PR );
1.39 store_spreg( R_ECX, REG_OFFSET(pc) );
1.40 sh4_x86.in_delay_slot = TRUE;
1.41 - sh4_x86_translate_instruction(pc+2);
1.42 + sh4_translate_instruction(pc+2);
1.43 exit_block_pcset(pc+2);
1.44 sh4_x86.branch_taken = TRUE;
1.45 return 4;
1.46 @@ -915,7 +915,7 @@
1.47 sh4_x86.priv_checked = FALSE;
1.48 sh4_x86.fpuen_checked = FALSE;
1.49 sh4_x86.tstate = TSTATE_NONE;
1.50 - sh4_x86_translate_instruction(pc+2);
1.51 + sh4_translate_instruction(pc+2);
1.52 exit_block_pcset(pc+2);
1.53 sh4_x86.branch_taken = TRUE;
1.54 return 4;
1.55 @@ -2062,7 +2062,7 @@
1.56 load_reg( R_ECX, Rn );
1.57 store_spreg( R_ECX, REG_OFFSET(pc) );
1.58 sh4_x86.in_delay_slot = TRUE;
1.59 - sh4_x86_translate_instruction(pc+2);
1.60 + sh4_translate_instruction(pc+2);
1.61 exit_block_pcset(pc+2);
1.62 sh4_x86.branch_taken = TRUE;
1.63 return 4;
1.64 @@ -2091,7 +2091,7 @@
1.65 load_reg( R_ECX, Rn );
1.66 store_spreg( R_ECX, REG_OFFSET(pc) );
1.67 sh4_x86.in_delay_slot = TRUE;
1.68 - sh4_x86_translate_instruction(pc+2);
1.69 + sh4_translate_instruction(pc+2);
1.70 exit_block_pcset(pc+2);
1.71 sh4_x86.branch_taken = TRUE;
1.72 return 4;
1.73 @@ -2551,11 +2551,11 @@
1.74 sh4_x86.tstate = TSTATE_E;
1.75 }
1.76 OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
1.77 - sh4_x86_translate_instruction(pc+2);
1.78 + sh4_translate_instruction(pc+2);
1.79 exit_block( disp + pc + 4, pc+4 );
1.80 // not taken
1.81 *patch = (xlat_output - ((uint8_t *)patch)) - 4;
1.82 - sh4_x86_translate_instruction(pc+2);
1.83 + sh4_translate_instruction(pc+2);
1.84 return 4;
1.85 }
1.86 }
1.87 @@ -2572,11 +2572,11 @@
1.88 sh4_x86.tstate = TSTATE_E;
1.89 }
1.90 OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
1.91 - sh4_x86_translate_instruction(pc+2);
1.92 + sh4_translate_instruction(pc+2);
1.93 exit_block( disp + pc + 4, pc+4 );
1.94 // not taken
1.95 *patch = (xlat_output - ((uint8_t *)patch)) - 4;
1.96 - sh4_x86_translate_instruction(pc+2);
1.97 + sh4_translate_instruction(pc+2);
1.98 return 4;
1.99 }
1.100 }
1.101 @@ -2606,7 +2606,7 @@
1.102 SLOTILLEGAL();
1.103 } else {
1.104 sh4_x86.in_delay_slot = TRUE;
1.105 - sh4_x86_translate_instruction( pc + 2 );
1.106 + sh4_translate_instruction( pc + 2 );
1.107 exit_block( disp + pc + 4, pc+4 );
1.108 sh4_x86.branch_taken = TRUE;
1.109 return 4;
1.110 @@ -2622,7 +2622,7 @@
1.111 load_imm32( R_EAX, pc + 4 );
1.112 store_spreg( R_EAX, R_PR );
1.113 sh4_x86.in_delay_slot = TRUE;
1.114 - sh4_x86_translate_instruction( pc + 2 );
1.115 + sh4_translate_instruction( pc + 2 );
1.116 exit_block( disp + pc + 4, pc+4 );
1.117 sh4_x86.branch_taken = TRUE;
1.118 return 4;
.