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lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 417:bd927df302a9
prev416:714df603c869
next502:c4ecae2b1b5e
author nkeynes
date Thu Oct 04 08:47:27 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Suppress redundant T flag loads
Tweak run_slice for performance
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.c Wed Oct 03 12:19:03 2007 +0000
1.2 +++ b/src/sh4/sh4x86.c Thu Oct 04 08:47:27 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4x86.c,v 1.17 2007-10-03 12:19:03 nkeynes Exp $
1.6 + * $Id: sh4x86.c,v 1.18 2007-10-04 08:47:27 nkeynes Exp $
1.7 *
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -25,6 +25,7 @@
1.11 #define DEBUG_JUMPS 1
1.12 #endif
1.13
1.14 +#include "sh4/xltcache.h"
1.15 #include "sh4/sh4core.h"
1.16 #include "sh4/sh4trans.h"
1.17 #include "sh4/sh4mmio.h"
1.18 @@ -44,6 +45,7 @@
1.19 gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
1.20 gboolean branch_taken; /* true if we branched unconditionally */
1.21 uint32_t block_start_pc;
1.22 + int tstate;
1.23
1.24 /* Allocated memory for the (block-wide) back-patch list */
1.25 uint32_t **backpatch_list;
1.26 @@ -51,6 +53,28 @@
1.27 uint32_t backpatch_size;
1.28 };
1.29
1.30 +#define TSTATE_NONE -1
1.31 +#define TSTATE_O 0
1.32 +#define TSTATE_C 2
1.33 +#define TSTATE_E 4
1.34 +#define TSTATE_NE 5
1.35 +#define TSTATE_G 0xF
1.36 +#define TSTATE_GE 0xD
1.37 +#define TSTATE_A 7
1.38 +#define TSTATE_AE 3
1.39 +
1.40 +/** Branch if T is set (either in the current cflags, or in sh4r.t) */
1.41 +#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
1.42 + CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
1.43 + OP(0x70+sh4_x86.tstate); OP(rel8); \
1.44 + MARK_JMP(rel8,label)
1.45 +/** Branch if T is clear (either in the current cflags or in sh4r.t) */
1.46 +#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
1.47 + CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
1.48 + OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
1.49 + MARK_JMP(rel8, label)
1.50 +
1.51 +
1.52 #define EXIT_DATA_ADDR_READ 0
1.53 #define EXIT_DATA_ADDR_WRITE 7
1.54 #define EXIT_ILLEGAL 14
1.55 @@ -403,6 +427,7 @@
1.56 sh4_x86.branch_taken = FALSE;
1.57 sh4_x86.backpatch_posn = 0;
1.58 sh4_x86.block_start_pc = pc;
1.59 + sh4_x86.tstate = TSTATE_NONE;
1.60 }
1.61
1.62 /**
1.63 @@ -427,9 +452,10 @@
1.64 */
1.65 void exit_block_pcset( pc )
1.66 {
1.67 - XOR_r32_r32( R_EAX, R_EAX ); // 2
1.68 load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
1.69 ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
1.70 + load_spreg( R_EAX, REG_OFFSET(pc) );
1.71 + call_func1(xlat_get_code,R_EAX);
1.72 POP_r32(R_EBP);
1.73 RET();
1.74 }
1.75 @@ -462,20 +488,20 @@
1.76 JMP_TARGET(target3);
1.77 JMP_TARGET(target4);
1.78 JMP_TARGET(target5);
1.79 + // Raise exception
1.80 load_spreg( R_ECX, REG_OFFSET(pc) );
1.81 ADD_r32_r32( R_EDX, R_ECX );
1.82 ADD_r32_r32( R_EDX, R_ECX );
1.83 store_spreg( R_ECX, REG_OFFSET(pc) );
1.84 MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
1.85 - load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
1.86 MUL_r32( R_EDX );
1.87 - ADD_r32_r32( R_EAX, R_ECX );
1.88 - store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
1.89 + ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
1.90
1.91 load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
1.92 CALL_r32( R_EAX ); // 2
1.93 ADD_imm8s_r32( 4, R_ESP );
1.94 - XOR_r32_r32( R_EAX, R_EAX );
1.95 + load_spreg( R_EAX, REG_OFFSET(pc) );
1.96 + call_func1(xlat_get_code,R_EAX);
1.97 POP_r32(R_EBP);
1.98 RET();
1.99
1.100 @@ -530,6 +556,7 @@
1.101 check_priv();
1.102 call_func0(sh4_read_sr);
1.103 store_reg( R_EAX, Rn );
1.104 + sh4_x86.tstate = TSTATE_NONE;
1.105 }
1.106 break;
1.107 case 0x1:
1.108 @@ -545,6 +572,7 @@
1.109 check_priv();
1.110 load_spreg( R_EAX, R_VBR );
1.111 store_reg( R_EAX, Rn );
1.112 + sh4_x86.tstate = TSTATE_NONE;
1.113 }
1.114 break;
1.115 case 0x3:
1.116 @@ -553,6 +581,7 @@
1.117 check_priv();
1.118 load_spreg( R_EAX, R_SSR );
1.119 store_reg( R_EAX, Rn );
1.120 + sh4_x86.tstate = TSTATE_NONE;
1.121 }
1.122 break;
1.123 case 0x4:
1.124 @@ -561,6 +590,7 @@
1.125 check_priv();
1.126 load_spreg( R_EAX, R_SPC );
1.127 store_reg( R_EAX, Rn );
1.128 + sh4_x86.tstate = TSTATE_NONE;
1.129 }
1.130 break;
1.131 default:
1.132 @@ -574,6 +604,7 @@
1.133 check_priv();
1.134 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
1.135 store_reg( R_EAX, Rn );
1.136 + sh4_x86.tstate = TSTATE_NONE;
1.137 }
1.138 break;
1.139 }
1.140 @@ -591,6 +622,7 @@
1.141 ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
1.142 store_spreg( R_ECX, REG_OFFSET(pc) );
1.143 sh4_x86.in_delay_slot = TRUE;
1.144 + sh4_x86.tstate = TSTATE_NONE;
1.145 sh4_x86_translate_instruction( pc + 2 );
1.146 exit_block_pcset(pc+2);
1.147 sh4_x86.branch_taken = TRUE;
1.148 @@ -608,6 +640,7 @@
1.149 ADD_imm32_r32( pc + 4, R_EAX );
1.150 store_spreg( R_EAX, REG_OFFSET(pc) );
1.151 sh4_x86.in_delay_slot = TRUE;
1.152 + sh4_x86.tstate = TSTATE_NONE;
1.153 sh4_x86_translate_instruction( pc + 2 );
1.154 exit_block_pcset(pc+2);
1.155 sh4_x86.branch_taken = TRUE;
1.156 @@ -626,6 +659,7 @@
1.157 call_func0( sh4_flush_store_queue );
1.158 JMP_TARGET(end);
1.159 ADD_imm8s_r32( 4, R_ESP );
1.160 + sh4_x86.tstate = TSTATE_NONE;
1.161 }
1.162 break;
1.163 case 0x9:
1.164 @@ -651,6 +685,7 @@
1.165 precheck();
1.166 check_walign32( R_ECX );
1.167 MEM_WRITE_LONG( R_ECX, R_EAX );
1.168 + sh4_x86.tstate = TSTATE_NONE;
1.169 }
1.170 break;
1.171 default:
1.172 @@ -666,6 +701,7 @@
1.173 ADD_r32_r32( R_EAX, R_ECX );
1.174 load_reg( R_EAX, Rm );
1.175 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.176 + sh4_x86.tstate = TSTATE_NONE;
1.177 }
1.178 break;
1.179 case 0x5:
1.180 @@ -678,6 +714,7 @@
1.181 check_walign16( R_ECX );
1.182 load_reg( R_EAX, Rm );
1.183 MEM_WRITE_WORD( R_ECX, R_EAX );
1.184 + sh4_x86.tstate = TSTATE_NONE;
1.185 }
1.186 break;
1.187 case 0x6:
1.188 @@ -690,6 +727,7 @@
1.189 check_walign32( R_ECX );
1.190 load_reg( R_EAX, Rm );
1.191 MEM_WRITE_LONG( R_ECX, R_EAX );
1.192 + sh4_x86.tstate = TSTATE_NONE;
1.193 }
1.194 break;
1.195 case 0x7:
1.196 @@ -699,6 +737,7 @@
1.197 load_reg( R_ECX, Rn );
1.198 MUL_r32( R_ECX );
1.199 store_spreg( R_EAX, R_MACL );
1.200 + sh4_x86.tstate = TSTATE_NONE;
1.201 }
1.202 break;
1.203 case 0x8:
1.204 @@ -707,12 +746,14 @@
1.205 { /* CLRT */
1.206 CLC();
1.207 SETC_t();
1.208 + sh4_x86.tstate = TSTATE_C;
1.209 }
1.210 break;
1.211 case 0x1:
1.212 { /* SETT */
1.213 STC();
1.214 SETC_t();
1.215 + sh4_x86.tstate = TSTATE_C;
1.216 }
1.217 break;
1.218 case 0x2:
1.219 @@ -720,6 +761,7 @@
1.220 XOR_r32_r32(R_EAX, R_EAX);
1.221 store_spreg( R_EAX, R_MACL );
1.222 store_spreg( R_EAX, R_MACH );
1.223 + sh4_x86.tstate = TSTATE_NONE;
1.224 }
1.225 break;
1.226 case 0x3:
1.227 @@ -730,12 +772,14 @@
1.228 { /* CLRS */
1.229 CLC();
1.230 SETC_sh4r(R_S);
1.231 + sh4_x86.tstate = TSTATE_C;
1.232 }
1.233 break;
1.234 case 0x5:
1.235 { /* SETS */
1.236 STC();
1.237 SETC_sh4r(R_S);
1.238 + sh4_x86.tstate = TSTATE_C;
1.239 }
1.240 break;
1.241 default:
1.242 @@ -756,6 +800,7 @@
1.243 store_spreg( R_EAX, R_Q );
1.244 store_spreg( R_EAX, R_M );
1.245 store_spreg( R_EAX, R_T );
1.246 + sh4_x86.tstate = TSTATE_C; // works for DIV1
1.247 }
1.248 break;
1.249 case 0x2:
1.250 @@ -799,6 +844,7 @@
1.251 check_priv();
1.252 load_spreg( R_EAX, R_SGR );
1.253 store_reg( R_EAX, Rn );
1.254 + sh4_x86.tstate = TSTATE_NONE;
1.255 }
1.256 break;
1.257 case 0x5:
1.258 @@ -821,6 +867,7 @@
1.259 check_priv();
1.260 load_spreg( R_EAX, R_DBR );
1.261 store_reg( R_EAX, Rn );
1.262 + sh4_x86.tstate = TSTATE_NONE;
1.263 }
1.264 break;
1.265 default:
1.266 @@ -849,6 +896,7 @@
1.267 { /* SLEEP */
1.268 check_priv();
1.269 call_func0( sh4_sleep );
1.270 + sh4_x86.tstate = TSTATE_NONE;
1.271 sh4_x86.in_delay_slot = FALSE;
1.272 return 2;
1.273 }
1.274 @@ -866,6 +914,7 @@
1.275 sh4_x86.in_delay_slot = TRUE;
1.276 sh4_x86.priv_checked = FALSE;
1.277 sh4_x86.fpuen_checked = FALSE;
1.278 + sh4_x86.tstate = TSTATE_NONE;
1.279 sh4_x86_translate_instruction(pc+2);
1.280 exit_block_pcset(pc+2);
1.281 sh4_x86.branch_taken = TRUE;
1.282 @@ -886,6 +935,7 @@
1.283 ADD_r32_r32( R_EAX, R_ECX );
1.284 MEM_READ_BYTE( R_ECX, R_EAX );
1.285 store_reg( R_EAX, Rn );
1.286 + sh4_x86.tstate = TSTATE_NONE;
1.287 }
1.288 break;
1.289 case 0xD:
1.290 @@ -898,6 +948,7 @@
1.291 check_ralign16( R_ECX );
1.292 MEM_READ_WORD( R_ECX, R_EAX );
1.293 store_reg( R_EAX, Rn );
1.294 + sh4_x86.tstate = TSTATE_NONE;
1.295 }
1.296 break;
1.297 case 0xE:
1.298 @@ -910,6 +961,7 @@
1.299 check_ralign32( R_ECX );
1.300 MEM_READ_LONG( R_ECX, R_EAX );
1.301 store_reg( R_EAX, Rn );
1.302 + sh4_x86.tstate = TSTATE_NONE;
1.303 }
1.304 break;
1.305 case 0xF:
1.306 @@ -936,6 +988,7 @@
1.307 JE_rel8( 7, nosat );
1.308 call_func0( signsat48 );
1.309 JMP_TARGET( nosat );
1.310 + sh4_x86.tstate = TSTATE_NONE;
1.311 }
1.312 break;
1.313 default:
1.314 @@ -952,6 +1005,7 @@
1.315 precheck();
1.316 check_walign32( R_ECX );
1.317 MEM_WRITE_LONG( R_ECX, R_EAX );
1.318 + sh4_x86.tstate = TSTATE_NONE;
1.319 }
1.320 break;
1.321 case 0x2:
1.322 @@ -962,6 +1016,7 @@
1.323 load_reg( R_EAX, Rm );
1.324 load_reg( R_ECX, Rn );
1.325 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.326 + sh4_x86.tstate = TSTATE_NONE;
1.327 }
1.328 break;
1.329 case 0x1:
1.330 @@ -972,6 +1027,7 @@
1.331 check_walign16( R_ECX );
1.332 load_reg( R_EAX, Rm );
1.333 MEM_WRITE_WORD( R_ECX, R_EAX );
1.334 + sh4_x86.tstate = TSTATE_NONE;
1.335 }
1.336 break;
1.337 case 0x2:
1.338 @@ -982,6 +1038,7 @@
1.339 precheck();
1.340 check_walign32(R_ECX);
1.341 MEM_WRITE_LONG( R_ECX, R_EAX );
1.342 + sh4_x86.tstate = TSTATE_NONE;
1.343 }
1.344 break;
1.345 case 0x4:
1.346 @@ -992,6 +1049,7 @@
1.347 ADD_imm8s_r32( -1, R_ECX );
1.348 store_reg( R_ECX, Rn );
1.349 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.350 + sh4_x86.tstate = TSTATE_NONE;
1.351 }
1.352 break;
1.353 case 0x5:
1.354 @@ -1004,6 +1062,7 @@
1.355 ADD_imm8s_r32( -2, R_ECX );
1.356 store_reg( R_ECX, Rn );
1.357 MEM_WRITE_WORD( R_ECX, R_EAX );
1.358 + sh4_x86.tstate = TSTATE_NONE;
1.359 }
1.360 break;
1.361 case 0x6:
1.362 @@ -1016,6 +1075,7 @@
1.363 ADD_imm8s_r32( -4, R_ECX );
1.364 store_reg( R_ECX, Rn );
1.365 MEM_WRITE_LONG( R_ECX, R_EAX );
1.366 + sh4_x86.tstate = TSTATE_NONE;
1.367 }
1.368 break;
1.369 case 0x7:
1.370 @@ -1029,6 +1089,7 @@
1.371 store_spreg( R_ECX, R_Q );
1.372 CMP_r32_r32( R_EAX, R_ECX );
1.373 SETNE_t();
1.374 + sh4_x86.tstate = TSTATE_NE;
1.375 }
1.376 break;
1.377 case 0x8:
1.378 @@ -1038,6 +1099,7 @@
1.379 load_reg( R_ECX, Rn );
1.380 TEST_r32_r32( R_EAX, R_ECX );
1.381 SETE_t();
1.382 + sh4_x86.tstate = TSTATE_E;
1.383 }
1.384 break;
1.385 case 0x9:
1.386 @@ -1047,6 +1109,7 @@
1.387 load_reg( R_ECX, Rn );
1.388 AND_r32_r32( R_EAX, R_ECX );
1.389 store_reg( R_ECX, Rn );
1.390 + sh4_x86.tstate = TSTATE_NONE;
1.391 }
1.392 break;
1.393 case 0xA:
1.394 @@ -1056,6 +1119,7 @@
1.395 load_reg( R_ECX, Rn );
1.396 XOR_r32_r32( R_EAX, R_ECX );
1.397 store_reg( R_ECX, Rn );
1.398 + sh4_x86.tstate = TSTATE_NONE;
1.399 }
1.400 break;
1.401 case 0xB:
1.402 @@ -1065,6 +1129,7 @@
1.403 load_reg( R_ECX, Rn );
1.404 OR_r32_r32( R_EAX, R_ECX );
1.405 store_reg( R_ECX, Rn );
1.406 + sh4_x86.tstate = TSTATE_NONE;
1.407 }
1.408 break;
1.409 case 0xC:
1.410 @@ -1085,6 +1150,7 @@
1.411 JMP_TARGET(target2);
1.412 JMP_TARGET(target3);
1.413 SETE_t();
1.414 + sh4_x86.tstate = TSTATE_E;
1.415 }
1.416 break;
1.417 case 0xD:
1.418 @@ -1096,6 +1162,7 @@
1.419 SHR_imm8_r32( 16, R_ECX );
1.420 OR_r32_r32( R_EAX, R_ECX );
1.421 store_reg( R_ECX, Rn );
1.422 + sh4_x86.tstate = TSTATE_NONE;
1.423 }
1.424 break;
1.425 case 0xE:
1.426 @@ -1105,6 +1172,7 @@
1.427 load_reg16u( R_ECX, Rn );
1.428 MUL_r32( R_ECX );
1.429 store_spreg( R_EAX, R_MACL );
1.430 + sh4_x86.tstate = TSTATE_NONE;
1.431 }
1.432 break;
1.433 case 0xF:
1.434 @@ -1114,6 +1182,7 @@
1.435 load_reg16s( R_ECX, Rn );
1.436 MUL_r32( R_ECX );
1.437 store_spreg( R_EAX, R_MACL );
1.438 + sh4_x86.tstate = TSTATE_NONE;
1.439 }
1.440 break;
1.441 default:
1.442 @@ -1130,6 +1199,7 @@
1.443 load_reg( R_ECX, Rn );
1.444 CMP_r32_r32( R_EAX, R_ECX );
1.445 SETE_t();
1.446 + sh4_x86.tstate = TSTATE_E;
1.447 }
1.448 break;
1.449 case 0x2:
1.450 @@ -1139,6 +1209,7 @@
1.451 load_reg( R_ECX, Rn );
1.452 CMP_r32_r32( R_EAX, R_ECX );
1.453 SETAE_t();
1.454 + sh4_x86.tstate = TSTATE_AE;
1.455 }
1.456 break;
1.457 case 0x3:
1.458 @@ -1148,6 +1219,7 @@
1.459 load_reg( R_ECX, Rn );
1.460 CMP_r32_r32( R_EAX, R_ECX );
1.461 SETGE_t();
1.462 + sh4_x86.tstate = TSTATE_GE;
1.463 }
1.464 break;
1.465 case 0x4:
1.466 @@ -1155,7 +1227,9 @@
1.467 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.468 load_spreg( R_ECX, R_M );
1.469 load_reg( R_EAX, Rn );
1.470 - LDC_t();
1.471 + if( sh4_x86.tstate != TSTATE_C ) {
1.472 + LDC_t();
1.473 + }
1.474 RCL1_r32( R_EAX );
1.475 SETC_r8( R_DL ); // Q'
1.476 CMP_sh4r_r32( R_Q, R_ECX );
1.477 @@ -1173,6 +1247,7 @@
1.478 XOR_imm8s_r32( 1, R_AL ); // T = !Q'
1.479 MOVZX_r8_r32( R_AL, R_EAX );
1.480 store_spreg( R_EAX, R_T );
1.481 + sh4_x86.tstate = TSTATE_NONE;
1.482 }
1.483 break;
1.484 case 0x5:
1.485 @@ -1182,7 +1257,8 @@
1.486 load_reg( R_ECX, Rn );
1.487 MUL_r32(R_ECX);
1.488 store_spreg( R_EDX, R_MACH );
1.489 - store_spreg( R_EAX, R_MACL );
1.490 + store_spreg( R_EAX, R_MACL );
1.491 + sh4_x86.tstate = TSTATE_NONE;
1.492 }
1.493 break;
1.494 case 0x6:
1.495 @@ -1192,6 +1268,7 @@
1.496 load_reg( R_ECX, Rn );
1.497 CMP_r32_r32( R_EAX, R_ECX );
1.498 SETA_t();
1.499 + sh4_x86.tstate = TSTATE_A;
1.500 }
1.501 break;
1.502 case 0x7:
1.503 @@ -1201,6 +1278,7 @@
1.504 load_reg( R_ECX, Rn );
1.505 CMP_r32_r32( R_EAX, R_ECX );
1.506 SETG_t();
1.507 + sh4_x86.tstate = TSTATE_G;
1.508 }
1.509 break;
1.510 case 0x8:
1.511 @@ -1210,6 +1288,7 @@
1.512 load_reg( R_ECX, Rn );
1.513 SUB_r32_r32( R_EAX, R_ECX );
1.514 store_reg( R_ECX, Rn );
1.515 + sh4_x86.tstate = TSTATE_NONE;
1.516 }
1.517 break;
1.518 case 0xA:
1.519 @@ -1217,10 +1296,13 @@
1.520 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.521 load_reg( R_EAX, Rm );
1.522 load_reg( R_ECX, Rn );
1.523 - LDC_t();
1.524 + if( sh4_x86.tstate != TSTATE_C ) {
1.525 + LDC_t();
1.526 + }
1.527 SBB_r32_r32( R_EAX, R_ECX );
1.528 store_reg( R_ECX, Rn );
1.529 SETC_t();
1.530 + sh4_x86.tstate = TSTATE_C;
1.531 }
1.532 break;
1.533 case 0xB:
1.534 @@ -1231,6 +1313,7 @@
1.535 SUB_r32_r32( R_EAX, R_ECX );
1.536 store_reg( R_ECX, Rn );
1.537 SETO_t();
1.538 + sh4_x86.tstate = TSTATE_O;
1.539 }
1.540 break;
1.541 case 0xC:
1.542 @@ -1240,6 +1323,7 @@
1.543 load_reg( R_ECX, Rn );
1.544 ADD_r32_r32( R_EAX, R_ECX );
1.545 store_reg( R_ECX, Rn );
1.546 + sh4_x86.tstate = TSTATE_NONE;
1.547 }
1.548 break;
1.549 case 0xD:
1.550 @@ -1250,17 +1334,21 @@
1.551 IMUL_r32(R_ECX);
1.552 store_spreg( R_EDX, R_MACH );
1.553 store_spreg( R_EAX, R_MACL );
1.554 + sh4_x86.tstate = TSTATE_NONE;
1.555 }
1.556 break;
1.557 case 0xE:
1.558 { /* ADDC Rm, Rn */
1.559 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.560 + if( sh4_x86.tstate != TSTATE_C ) {
1.561 + LDC_t();
1.562 + }
1.563 load_reg( R_EAX, Rm );
1.564 load_reg( R_ECX, Rn );
1.565 - LDC_t();
1.566 ADC_r32_r32( R_EAX, R_ECX );
1.567 store_reg( R_ECX, Rn );
1.568 SETC_t();
1.569 + sh4_x86.tstate = TSTATE_C;
1.570 }
1.571 break;
1.572 case 0xF:
1.573 @@ -1271,6 +1359,7 @@
1.574 ADD_r32_r32( R_EAX, R_ECX );
1.575 store_reg( R_ECX, Rn );
1.576 SETO_t();
1.577 + sh4_x86.tstate = TSTATE_O;
1.578 }
1.579 break;
1.580 default:
1.581 @@ -1289,6 +1378,7 @@
1.582 SHL1_r32( R_EAX );
1.583 SETC_t();
1.584 store_reg( R_EAX, Rn );
1.585 + sh4_x86.tstate = TSTATE_C;
1.586 }
1.587 break;
1.588 case 0x1:
1.589 @@ -1298,6 +1388,7 @@
1.590 ADD_imm8s_r32( -1, R_EAX );
1.591 store_reg( R_EAX, Rn );
1.592 SETE_t();
1.593 + sh4_x86.tstate = TSTATE_E;
1.594 }
1.595 break;
1.596 case 0x2:
1.597 @@ -1307,6 +1398,7 @@
1.598 SHL1_r32( R_EAX );
1.599 SETC_t();
1.600 store_reg( R_EAX, Rn );
1.601 + sh4_x86.tstate = TSTATE_C;
1.602 }
1.603 break;
1.604 default:
1.605 @@ -1323,6 +1415,7 @@
1.606 SHR1_r32( R_EAX );
1.607 SETC_t();
1.608 store_reg( R_EAX, Rn );
1.609 + sh4_x86.tstate = TSTATE_C;
1.610 }
1.611 break;
1.612 case 0x1:
1.613 @@ -1331,6 +1424,7 @@
1.614 load_reg( R_EAX, Rn );
1.615 CMP_imm8s_r32( 0, R_EAX );
1.616 SETGE_t();
1.617 + sh4_x86.tstate = TSTATE_GE;
1.618 }
1.619 break;
1.620 case 0x2:
1.621 @@ -1340,6 +1434,7 @@
1.622 SAR1_r32( R_EAX );
1.623 SETC_t();
1.624 store_reg( R_EAX, Rn );
1.625 + sh4_x86.tstate = TSTATE_C;
1.626 }
1.627 break;
1.628 default:
1.629 @@ -1359,6 +1454,7 @@
1.630 store_reg( R_ECX, Rn );
1.631 load_spreg( R_EAX, R_MACH );
1.632 MEM_WRITE_LONG( R_ECX, R_EAX );
1.633 + sh4_x86.tstate = TSTATE_NONE;
1.634 }
1.635 break;
1.636 case 0x1:
1.637 @@ -1371,6 +1467,7 @@
1.638 store_reg( R_ECX, Rn );
1.639 load_spreg( R_EAX, R_MACL );
1.640 MEM_WRITE_LONG( R_ECX, R_EAX );
1.641 + sh4_x86.tstate = TSTATE_NONE;
1.642 }
1.643 break;
1.644 case 0x2:
1.645 @@ -1383,6 +1480,7 @@
1.646 store_reg( R_ECX, Rn );
1.647 load_spreg( R_EAX, R_PR );
1.648 MEM_WRITE_LONG( R_ECX, R_EAX );
1.649 + sh4_x86.tstate = TSTATE_NONE;
1.650 }
1.651 break;
1.652 case 0x3:
1.653 @@ -1396,6 +1494,7 @@
1.654 store_reg( R_ECX, Rn );
1.655 load_spreg( R_EAX, R_SGR );
1.656 MEM_WRITE_LONG( R_ECX, R_EAX );
1.657 + sh4_x86.tstate = TSTATE_NONE;
1.658 }
1.659 break;
1.660 case 0x5:
1.661 @@ -1408,6 +1507,7 @@
1.662 store_reg( R_ECX, Rn );
1.663 load_spreg( R_EAX, R_FPUL );
1.664 MEM_WRITE_LONG( R_ECX, R_EAX );
1.665 + sh4_x86.tstate = TSTATE_NONE;
1.666 }
1.667 break;
1.668 case 0x6:
1.669 @@ -1420,6 +1520,7 @@
1.670 store_reg( R_ECX, Rn );
1.671 load_spreg( R_EAX, R_FPSCR );
1.672 MEM_WRITE_LONG( R_ECX, R_EAX );
1.673 + sh4_x86.tstate = TSTATE_NONE;
1.674 }
1.675 break;
1.676 case 0xF:
1.677 @@ -1433,6 +1534,7 @@
1.678 store_reg( R_ECX, Rn );
1.679 load_spreg( R_EAX, R_DBR );
1.680 MEM_WRITE_LONG( R_ECX, R_EAX );
1.681 + sh4_x86.tstate = TSTATE_NONE;
1.682 }
1.683 break;
1.684 default:
1.685 @@ -1455,6 +1557,7 @@
1.686 ADD_imm8s_r32( -4, R_ECX );
1.687 store_reg( R_ECX, Rn );
1.688 MEM_WRITE_LONG( R_ECX, R_EAX );
1.689 + sh4_x86.tstate = TSTATE_NONE;
1.690 }
1.691 break;
1.692 case 0x1:
1.693 @@ -1467,6 +1570,7 @@
1.694 store_reg( R_ECX, Rn );
1.695 load_spreg( R_EAX, R_GBR );
1.696 MEM_WRITE_LONG( R_ECX, R_EAX );
1.697 + sh4_x86.tstate = TSTATE_NONE;
1.698 }
1.699 break;
1.700 case 0x2:
1.701 @@ -1480,6 +1584,7 @@
1.702 store_reg( R_ECX, Rn );
1.703 load_spreg( R_EAX, R_VBR );
1.704 MEM_WRITE_LONG( R_ECX, R_EAX );
1.705 + sh4_x86.tstate = TSTATE_NONE;
1.706 }
1.707 break;
1.708 case 0x3:
1.709 @@ -1493,6 +1598,7 @@
1.710 store_reg( R_ECX, Rn );
1.711 load_spreg( R_EAX, R_SSR );
1.712 MEM_WRITE_LONG( R_ECX, R_EAX );
1.713 + sh4_x86.tstate = TSTATE_NONE;
1.714 }
1.715 break;
1.716 case 0x4:
1.717 @@ -1506,6 +1612,7 @@
1.718 store_reg( R_ECX, Rn );
1.719 load_spreg( R_EAX, R_SPC );
1.720 MEM_WRITE_LONG( R_ECX, R_EAX );
1.721 + sh4_x86.tstate = TSTATE_NONE;
1.722 }
1.723 break;
1.724 default:
1.725 @@ -1524,6 +1631,7 @@
1.726 store_reg( R_ECX, Rn );
1.727 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
1.728 MEM_WRITE_LONG( R_ECX, R_EAX );
1.729 + sh4_x86.tstate = TSTATE_NONE;
1.730 }
1.731 break;
1.732 }
1.733 @@ -1537,16 +1645,20 @@
1.734 ROL1_r32( R_EAX );
1.735 store_reg( R_EAX, Rn );
1.736 SETC_t();
1.737 + sh4_x86.tstate = TSTATE_C;
1.738 }
1.739 break;
1.740 case 0x2:
1.741 { /* ROTCL Rn */
1.742 uint32_t Rn = ((ir>>8)&0xF);
1.743 load_reg( R_EAX, Rn );
1.744 - LDC_t();
1.745 + if( sh4_x86.tstate != TSTATE_C ) {
1.746 + LDC_t();
1.747 + }
1.748 RCL1_r32( R_EAX );
1.749 store_reg( R_EAX, Rn );
1.750 SETC_t();
1.751 + sh4_x86.tstate = TSTATE_C;
1.752 }
1.753 break;
1.754 default:
1.755 @@ -1563,6 +1675,7 @@
1.756 ROR1_r32( R_EAX );
1.757 store_reg( R_EAX, Rn );
1.758 SETC_t();
1.759 + sh4_x86.tstate = TSTATE_C;
1.760 }
1.761 break;
1.762 case 0x1:
1.763 @@ -1571,16 +1684,20 @@
1.764 load_reg( R_EAX, Rn );
1.765 CMP_imm8s_r32( 0, R_EAX );
1.766 SETG_t();
1.767 + sh4_x86.tstate = TSTATE_G;
1.768 }
1.769 break;
1.770 case 0x2:
1.771 { /* ROTCR Rn */
1.772 uint32_t Rn = ((ir>>8)&0xF);
1.773 load_reg( R_EAX, Rn );
1.774 - LDC_t();
1.775 + if( sh4_x86.tstate != TSTATE_C ) {
1.776 + LDC_t();
1.777 + }
1.778 RCR1_r32( R_EAX );
1.779 store_reg( R_EAX, Rn );
1.780 SETC_t();
1.781 + sh4_x86.tstate = TSTATE_C;
1.782 }
1.783 break;
1.784 default:
1.785 @@ -1601,6 +1718,7 @@
1.786 store_reg( R_EAX, Rm );
1.787 MEM_READ_LONG( R_ECX, R_EAX );
1.788 store_spreg( R_EAX, R_MACH );
1.789 + sh4_x86.tstate = TSTATE_NONE;
1.790 }
1.791 break;
1.792 case 0x1:
1.793 @@ -1614,6 +1732,7 @@
1.794 store_reg( R_EAX, Rm );
1.795 MEM_READ_LONG( R_ECX, R_EAX );
1.796 store_spreg( R_EAX, R_MACL );
1.797 + sh4_x86.tstate = TSTATE_NONE;
1.798 }
1.799 break;
1.800 case 0x2:
1.801 @@ -1627,6 +1746,7 @@
1.802 store_reg( R_EAX, Rm );
1.803 MEM_READ_LONG( R_ECX, R_EAX );
1.804 store_spreg( R_EAX, R_PR );
1.805 + sh4_x86.tstate = TSTATE_NONE;
1.806 }
1.807 break;
1.808 case 0x3:
1.809 @@ -1641,6 +1761,7 @@
1.810 store_reg( R_EAX, Rm );
1.811 MEM_READ_LONG( R_ECX, R_EAX );
1.812 store_spreg( R_EAX, R_SGR );
1.813 + sh4_x86.tstate = TSTATE_NONE;
1.814 }
1.815 break;
1.816 case 0x5:
1.817 @@ -1654,6 +1775,7 @@
1.818 store_reg( R_EAX, Rm );
1.819 MEM_READ_LONG( R_ECX, R_EAX );
1.820 store_spreg( R_EAX, R_FPUL );
1.821 + sh4_x86.tstate = TSTATE_NONE;
1.822 }
1.823 break;
1.824 case 0x6:
1.825 @@ -1668,6 +1790,7 @@
1.826 MEM_READ_LONG( R_ECX, R_EAX );
1.827 store_spreg( R_EAX, R_FPSCR );
1.828 update_fr_bank( R_EAX );
1.829 + sh4_x86.tstate = TSTATE_NONE;
1.830 }
1.831 break;
1.832 case 0xF:
1.833 @@ -1682,6 +1805,7 @@
1.834 store_reg( R_EAX, Rm );
1.835 MEM_READ_LONG( R_ECX, R_EAX );
1.836 store_spreg( R_EAX, R_DBR );
1.837 + sh4_x86.tstate = TSTATE_NONE;
1.838 }
1.839 break;
1.840 default:
1.841 @@ -1710,6 +1834,7 @@
1.842 call_func1( sh4_write_sr, R_EAX );
1.843 sh4_x86.priv_checked = FALSE;
1.844 sh4_x86.fpuen_checked = FALSE;
1.845 + sh4_x86.tstate = TSTATE_NONE;
1.846 }
1.847 }
1.848 break;
1.849 @@ -1724,6 +1849,7 @@
1.850 store_reg( R_EAX, Rm );
1.851 MEM_READ_LONG( R_ECX, R_EAX );
1.852 store_spreg( R_EAX, R_GBR );
1.853 + sh4_x86.tstate = TSTATE_NONE;
1.854 }
1.855 break;
1.856 case 0x2:
1.857 @@ -1738,6 +1864,7 @@
1.858 store_reg( R_EAX, Rm );
1.859 MEM_READ_LONG( R_ECX, R_EAX );
1.860 store_spreg( R_EAX, R_VBR );
1.861 + sh4_x86.tstate = TSTATE_NONE;
1.862 }
1.863 break;
1.864 case 0x3:
1.865 @@ -1752,6 +1879,7 @@
1.866 store_reg( R_EAX, Rm );
1.867 MEM_READ_LONG( R_ECX, R_EAX );
1.868 store_spreg( R_EAX, R_SSR );
1.869 + sh4_x86.tstate = TSTATE_NONE;
1.870 }
1.871 break;
1.872 case 0x4:
1.873 @@ -1766,6 +1894,7 @@
1.874 store_reg( R_EAX, Rm );
1.875 MEM_READ_LONG( R_ECX, R_EAX );
1.876 store_spreg( R_EAX, R_SPC );
1.877 + sh4_x86.tstate = TSTATE_NONE;
1.878 }
1.879 break;
1.880 default:
1.881 @@ -1785,6 +1914,7 @@
1.882 store_reg( R_EAX, Rm );
1.883 MEM_READ_LONG( R_ECX, R_EAX );
1.884 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
1.885 + sh4_x86.tstate = TSTATE_NONE;
1.886 }
1.887 break;
1.888 }
1.889 @@ -1797,6 +1927,7 @@
1.890 load_reg( R_EAX, Rn );
1.891 SHL_imm8_r32( 2, R_EAX );
1.892 store_reg( R_EAX, Rn );
1.893 + sh4_x86.tstate = TSTATE_NONE;
1.894 }
1.895 break;
1.896 case 0x1:
1.897 @@ -1805,6 +1936,7 @@
1.898 load_reg( R_EAX, Rn );
1.899 SHL_imm8_r32( 8, R_EAX );
1.900 store_reg( R_EAX, Rn );
1.901 + sh4_x86.tstate = TSTATE_NONE;
1.902 }
1.903 break;
1.904 case 0x2:
1.905 @@ -1813,6 +1945,7 @@
1.906 load_reg( R_EAX, Rn );
1.907 SHL_imm8_r32( 16, R_EAX );
1.908 store_reg( R_EAX, Rn );
1.909 + sh4_x86.tstate = TSTATE_NONE;
1.910 }
1.911 break;
1.912 default:
1.913 @@ -1828,6 +1961,7 @@
1.914 load_reg( R_EAX, Rn );
1.915 SHR_imm8_r32( 2, R_EAX );
1.916 store_reg( R_EAX, Rn );
1.917 + sh4_x86.tstate = TSTATE_NONE;
1.918 }
1.919 break;
1.920 case 0x1:
1.921 @@ -1836,6 +1970,7 @@
1.922 load_reg( R_EAX, Rn );
1.923 SHR_imm8_r32( 8, R_EAX );
1.924 store_reg( R_EAX, Rn );
1.925 + sh4_x86.tstate = TSTATE_NONE;
1.926 }
1.927 break;
1.928 case 0x2:
1.929 @@ -1844,6 +1979,7 @@
1.930 load_reg( R_EAX, Rn );
1.931 SHR_imm8_r32( 16, R_EAX );
1.932 store_reg( R_EAX, Rn );
1.933 + sh4_x86.tstate = TSTATE_NONE;
1.934 }
1.935 break;
1.936 default:
1.937 @@ -1880,6 +2016,7 @@
1.938 check_priv();
1.939 load_reg( R_EAX, Rm );
1.940 store_spreg( R_EAX, R_SGR );
1.941 + sh4_x86.tstate = TSTATE_NONE;
1.942 }
1.943 break;
1.944 case 0x5:
1.945 @@ -1895,6 +2032,7 @@
1.946 load_reg( R_EAX, Rm );
1.947 store_spreg( R_EAX, R_FPSCR );
1.948 update_fr_bank( R_EAX );
1.949 + sh4_x86.tstate = TSTATE_NONE;
1.950 }
1.951 break;
1.952 case 0xF:
1.953 @@ -1903,6 +2041,7 @@
1.954 check_priv();
1.955 load_reg( R_EAX, Rm );
1.956 store_spreg( R_EAX, R_DBR );
1.957 + sh4_x86.tstate = TSTATE_NONE;
1.958 }
1.959 break;
1.960 default:
1.961 @@ -1940,6 +2079,7 @@
1.962 OR_imm8_r8( 0x80, R_AL );
1.963 load_reg( R_ECX, Rn );
1.964 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.965 + sh4_x86.tstate = TSTATE_NONE;
1.966 }
1.967 break;
1.968 case 0x2:
1.969 @@ -1988,6 +2128,7 @@
1.970 JMP_TARGET(end);
1.971 JMP_TARGET(end2);
1.972 store_reg( R_EAX, Rn );
1.973 + sh4_x86.tstate = TSTATE_NONE;
1.974 }
1.975 break;
1.976 case 0xD:
1.977 @@ -2014,6 +2155,7 @@
1.978 JMP_TARGET(end);
1.979 JMP_TARGET(end2);
1.980 store_reg( R_EAX, Rn );
1.981 + sh4_x86.tstate = TSTATE_NONE;
1.982 }
1.983 break;
1.984 case 0xE:
1.985 @@ -2031,6 +2173,7 @@
1.986 call_func1( sh4_write_sr, R_EAX );
1.987 sh4_x86.priv_checked = FALSE;
1.988 sh4_x86.fpuen_checked = FALSE;
1.989 + sh4_x86.tstate = TSTATE_NONE;
1.990 }
1.991 }
1.992 break;
1.993 @@ -2047,6 +2190,7 @@
1.994 check_priv();
1.995 load_reg( R_EAX, Rm );
1.996 store_spreg( R_EAX, R_VBR );
1.997 + sh4_x86.tstate = TSTATE_NONE;
1.998 }
1.999 break;
1.1000 case 0x3:
1.1001 @@ -2055,6 +2199,7 @@
1.1002 check_priv();
1.1003 load_reg( R_EAX, Rm );
1.1004 store_spreg( R_EAX, R_SSR );
1.1005 + sh4_x86.tstate = TSTATE_NONE;
1.1006 }
1.1007 break;
1.1008 case 0x4:
1.1009 @@ -2063,6 +2208,7 @@
1.1010 check_priv();
1.1011 load_reg( R_EAX, Rm );
1.1012 store_spreg( R_EAX, R_SPC );
1.1013 + sh4_x86.tstate = TSTATE_NONE;
1.1014 }
1.1015 break;
1.1016 default:
1.1017 @@ -2076,6 +2222,7 @@
1.1018 check_priv();
1.1019 load_reg( R_EAX, Rm );
1.1020 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
1.1021 + sh4_x86.tstate = TSTATE_NONE;
1.1022 }
1.1023 break;
1.1024 }
1.1025 @@ -2121,6 +2268,7 @@
1.1026 JMP_TARGET(end);
1.1027 JMP_TARGET(end2);
1.1028 JMP_TARGET(end3);
1.1029 + sh4_x86.tstate = TSTATE_NONE;
1.1030 }
1.1031 break;
1.1032 }
1.1033 @@ -2134,6 +2282,7 @@
1.1034 check_ralign32( R_ECX );
1.1035 MEM_READ_LONG( R_ECX, R_EAX );
1.1036 store_reg( R_EAX, Rn );
1.1037 + sh4_x86.tstate = TSTATE_NONE;
1.1038 }
1.1039 break;
1.1040 case 0x6:
1.1041 @@ -2144,6 +2293,7 @@
1.1042 load_reg( R_ECX, Rm );
1.1043 MEM_READ_BYTE( R_ECX, R_EAX );
1.1044 store_reg( R_EAX, Rn );
1.1045 + sh4_x86.tstate = TSTATE_NONE;
1.1046 }
1.1047 break;
1.1048 case 0x1:
1.1049 @@ -2154,6 +2304,7 @@
1.1050 check_ralign16( R_ECX );
1.1051 MEM_READ_WORD( R_ECX, R_EAX );
1.1052 store_reg( R_EAX, Rn );
1.1053 + sh4_x86.tstate = TSTATE_NONE;
1.1054 }
1.1055 break;
1.1056 case 0x2:
1.1057 @@ -2164,6 +2315,7 @@
1.1058 check_ralign32( R_ECX );
1.1059 MEM_READ_LONG( R_ECX, R_EAX );
1.1060 store_reg( R_EAX, Rn );
1.1061 + sh4_x86.tstate = TSTATE_NONE;
1.1062 }
1.1063 break;
1.1064 case 0x3:
1.1065 @@ -2182,6 +2334,7 @@
1.1066 store_reg( R_EAX, Rm );
1.1067 MEM_READ_BYTE( R_ECX, R_EAX );
1.1068 store_reg( R_EAX, Rn );
1.1069 + sh4_x86.tstate = TSTATE_NONE;
1.1070 }
1.1071 break;
1.1072 case 0x5:
1.1073 @@ -2195,6 +2348,7 @@
1.1074 store_reg( R_EAX, Rm );
1.1075 MEM_READ_WORD( R_ECX, R_EAX );
1.1076 store_reg( R_EAX, Rn );
1.1077 + sh4_x86.tstate = TSTATE_NONE;
1.1078 }
1.1079 break;
1.1080 case 0x6:
1.1081 @@ -2208,6 +2362,7 @@
1.1082 store_reg( R_EAX, Rm );
1.1083 MEM_READ_LONG( R_ECX, R_EAX );
1.1084 store_reg( R_EAX, Rn );
1.1085 + sh4_x86.tstate = TSTATE_NONE;
1.1086 }
1.1087 break;
1.1088 case 0x7:
1.1089 @@ -2216,6 +2371,7 @@
1.1090 load_reg( R_EAX, Rm );
1.1091 NOT_r32( R_EAX );
1.1092 store_reg( R_EAX, Rn );
1.1093 + sh4_x86.tstate = TSTATE_NONE;
1.1094 }
1.1095 break;
1.1096 case 0x8:
1.1097 @@ -2235,6 +2391,7 @@
1.1098 SHR_imm8_r32( 16, R_EAX );
1.1099 OR_r32_r32( R_EAX, R_ECX );
1.1100 store_reg( R_ECX, Rn );
1.1101 + sh4_x86.tstate = TSTATE_NONE;
1.1102 }
1.1103 break;
1.1104 case 0xA:
1.1105 @@ -2246,6 +2403,7 @@
1.1106 SBB_r32_r32( R_EAX, R_ECX );
1.1107 store_reg( R_ECX, Rn );
1.1108 SETC_t();
1.1109 + sh4_x86.tstate = TSTATE_C;
1.1110 }
1.1111 break;
1.1112 case 0xB:
1.1113 @@ -2254,6 +2412,7 @@
1.1114 load_reg( R_EAX, Rm );
1.1115 NEG_r32( R_EAX );
1.1116 store_reg( R_EAX, Rn );
1.1117 + sh4_x86.tstate = TSTATE_NONE;
1.1118 }
1.1119 break;
1.1120 case 0xC:
1.1121 @@ -2296,6 +2455,7 @@
1.1122 load_reg( R_EAX, Rn );
1.1123 ADD_imm8s_r32( imm, R_EAX );
1.1124 store_reg( R_EAX, Rn );
1.1125 + sh4_x86.tstate = TSTATE_NONE;
1.1126 }
1.1127 break;
1.1128 case 0x8:
1.1129 @@ -2307,6 +2467,7 @@
1.1130 load_reg( R_ECX, Rn );
1.1131 ADD_imm32_r32( disp, R_ECX );
1.1132 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.1133 + sh4_x86.tstate = TSTATE_NONE;
1.1134 }
1.1135 break;
1.1136 case 0x1:
1.1137 @@ -2318,6 +2479,7 @@
1.1138 precheck();
1.1139 check_walign16( R_ECX );
1.1140 MEM_WRITE_WORD( R_ECX, R_EAX );
1.1141 + sh4_x86.tstate = TSTATE_NONE;
1.1142 }
1.1143 break;
1.1144 case 0x4:
1.1145 @@ -2327,6 +2489,7 @@
1.1146 ADD_imm32_r32( disp, R_ECX );
1.1147 MEM_READ_BYTE( R_ECX, R_EAX );
1.1148 store_reg( R_EAX, 0 );
1.1149 + sh4_x86.tstate = TSTATE_NONE;
1.1150 }
1.1151 break;
1.1152 case 0x5:
1.1153 @@ -2338,6 +2501,7 @@
1.1154 check_ralign16( R_ECX );
1.1155 MEM_READ_WORD( R_ECX, R_EAX );
1.1156 store_reg( R_EAX, 0 );
1.1157 + sh4_x86.tstate = TSTATE_NONE;
1.1158 }
1.1159 break;
1.1160 case 0x8:
1.1161 @@ -2346,6 +2510,7 @@
1.1162 load_reg( R_EAX, 0 );
1.1163 CMP_imm8s_r32(imm, R_EAX);
1.1164 SETE_t();
1.1165 + sh4_x86.tstate = TSTATE_E;
1.1166 }
1.1167 break;
1.1168 case 0x9:
1.1169 @@ -2354,8 +2519,7 @@
1.1170 if( sh4_x86.in_delay_slot ) {
1.1171 SLOTILLEGAL();
1.1172 } else {
1.1173 - CMP_imm8s_sh4r( 0, R_T );
1.1174 - JE_rel8( 29, nottaken );
1.1175 + JF_rel8( 29, nottaken );
1.1176 exit_block( disp + pc + 4, pc+2 );
1.1177 JMP_TARGET(nottaken);
1.1178 return 2;
1.1179 @@ -2368,8 +2532,7 @@
1.1180 if( sh4_x86.in_delay_slot ) {
1.1181 SLOTILLEGAL();
1.1182 } else {
1.1183 - CMP_imm8s_sh4r( 0, R_T );
1.1184 - JNE_rel8( 29, nottaken );
1.1185 + JT_rel8( 29, nottaken );
1.1186 exit_block( disp + pc + 4, pc+2 );
1.1187 JMP_TARGET(nottaken);
1.1188 return 2;
1.1189 @@ -2383,8 +2546,11 @@
1.1190 SLOTILLEGAL();
1.1191 } else {
1.1192 sh4_x86.in_delay_slot = TRUE;
1.1193 - CMP_imm8s_sh4r( 0, R_T );
1.1194 - OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
1.1195 + if( sh4_x86.tstate == TSTATE_NONE ) {
1.1196 + CMP_imm8s_sh4r( 1, R_T );
1.1197 + sh4_x86.tstate = TSTATE_E;
1.1198 + }
1.1199 + OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
1.1200 sh4_x86_translate_instruction(pc+2);
1.1201 exit_block( disp + pc + 4, pc+4 );
1.1202 // not taken
1.1203 @@ -2401,8 +2567,11 @@
1.1204 SLOTILLEGAL();
1.1205 } else {
1.1206 sh4_x86.in_delay_slot = TRUE;
1.1207 - CMP_imm8s_sh4r( 0, R_T );
1.1208 - OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
1.1209 + if( sh4_x86.tstate == TSTATE_NONE ) {
1.1210 + CMP_imm8s_sh4r( 1, R_T );
1.1211 + sh4_x86.tstate = TSTATE_E;
1.1212 + }
1.1213 + OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
1.1214 sh4_x86_translate_instruction(pc+2);
1.1215 exit_block( disp + pc + 4, pc+4 );
1.1216 // not taken
1.1217 @@ -2426,6 +2595,7 @@
1.1218 load_imm32( R_ECX, pc + disp + 4 );
1.1219 MEM_READ_WORD( R_ECX, R_EAX );
1.1220 store_reg( R_EAX, Rn );
1.1221 + sh4_x86.tstate = TSTATE_NONE;
1.1222 }
1.1223 }
1.1224 break;
1.1225 @@ -2468,6 +2638,7 @@
1.1226 load_spreg( R_ECX, R_GBR );
1.1227 ADD_imm32_r32( disp, R_ECX );
1.1228 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.1229 + sh4_x86.tstate = TSTATE_NONE;
1.1230 }
1.1231 break;
1.1232 case 0x1:
1.1233 @@ -2479,6 +2650,7 @@
1.1234 precheck();
1.1235 check_walign16( R_ECX );
1.1236 MEM_WRITE_WORD( R_ECX, R_EAX );
1.1237 + sh4_x86.tstate = TSTATE_NONE;
1.1238 }
1.1239 break;
1.1240 case 0x2:
1.1241 @@ -2490,6 +2662,7 @@
1.1242 precheck();
1.1243 check_walign32( R_ECX );
1.1244 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1245 + sh4_x86.tstate = TSTATE_NONE;
1.1246 }
1.1247 break;
1.1248 case 0x3:
1.1249 @@ -2501,6 +2674,7 @@
1.1250 PUSH_imm32( imm );
1.1251 call_func0( sh4_raise_trap );
1.1252 ADD_imm8s_r32( 4, R_ESP );
1.1253 + sh4_x86.tstate = TSTATE_NONE;
1.1254 exit_block_pcset(pc);
1.1255 sh4_x86.branch_taken = TRUE;
1.1256 return 2;
1.1257 @@ -2514,6 +2688,7 @@
1.1258 ADD_imm32_r32( disp, R_ECX );
1.1259 MEM_READ_BYTE( R_ECX, R_EAX );
1.1260 store_reg( R_EAX, 0 );
1.1261 + sh4_x86.tstate = TSTATE_NONE;
1.1262 }
1.1263 break;
1.1264 case 0x5:
1.1265 @@ -2525,6 +2700,7 @@
1.1266 check_ralign16( R_ECX );
1.1267 MEM_READ_WORD( R_ECX, R_EAX );
1.1268 store_reg( R_EAX, 0 );
1.1269 + sh4_x86.tstate = TSTATE_NONE;
1.1270 }
1.1271 break;
1.1272 case 0x6:
1.1273 @@ -2536,6 +2712,7 @@
1.1274 check_ralign32( R_ECX );
1.1275 MEM_READ_LONG( R_ECX, R_EAX );
1.1276 store_reg( R_EAX, 0 );
1.1277 + sh4_x86.tstate = TSTATE_NONE;
1.1278 }
1.1279 break;
1.1280 case 0x7:
1.1281 @@ -2555,6 +2732,7 @@
1.1282 load_reg( R_EAX, 0 );
1.1283 TEST_imm32_r32( imm, R_EAX );
1.1284 SETE_t();
1.1285 + sh4_x86.tstate = TSTATE_E;
1.1286 }
1.1287 break;
1.1288 case 0x9:
1.1289 @@ -2563,6 +2741,7 @@
1.1290 load_reg( R_EAX, 0 );
1.1291 AND_imm32_r32(imm, R_EAX);
1.1292 store_reg( R_EAX, 0 );
1.1293 + sh4_x86.tstate = TSTATE_NONE;
1.1294 }
1.1295 break;
1.1296 case 0xA:
1.1297 @@ -2571,6 +2750,7 @@
1.1298 load_reg( R_EAX, 0 );
1.1299 XOR_imm32_r32( imm, R_EAX );
1.1300 store_reg( R_EAX, 0 );
1.1301 + sh4_x86.tstate = TSTATE_NONE;
1.1302 }
1.1303 break;
1.1304 case 0xB:
1.1305 @@ -2579,6 +2759,7 @@
1.1306 load_reg( R_EAX, 0 );
1.1307 OR_imm32_r32(imm, R_EAX);
1.1308 store_reg( R_EAX, 0 );
1.1309 + sh4_x86.tstate = TSTATE_NONE;
1.1310 }
1.1311 break;
1.1312 case 0xC:
1.1313 @@ -2590,6 +2771,7 @@
1.1314 MEM_READ_BYTE( R_ECX, R_EAX );
1.1315 TEST_imm8_r8( imm, R_AL );
1.1316 SETE_t();
1.1317 + sh4_x86.tstate = TSTATE_E;
1.1318 }
1.1319 break;
1.1320 case 0xD:
1.1321 @@ -2603,6 +2785,7 @@
1.1322 POP_r32(R_ECX);
1.1323 AND_imm32_r32(imm, R_EAX );
1.1324 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.1325 + sh4_x86.tstate = TSTATE_NONE;
1.1326 }
1.1327 break;
1.1328 case 0xE:
1.1329 @@ -2616,6 +2799,7 @@
1.1330 POP_r32(R_ECX);
1.1331 XOR_imm32_r32( imm, R_EAX );
1.1332 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.1333 + sh4_x86.tstate = TSTATE_NONE;
1.1334 }
1.1335 break;
1.1336 case 0xF:
1.1337 @@ -2629,6 +2813,7 @@
1.1338 POP_r32(R_ECX);
1.1339 OR_imm32_r32(imm, R_EAX );
1.1340 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.1341 + sh4_x86.tstate = TSTATE_NONE;
1.1342 }
1.1343 break;
1.1344 }
1.1345 @@ -2648,6 +2833,7 @@
1.1346 MEM_READ_LONG( R_ECX, R_EAX );
1.1347 }
1.1348 store_reg( R_EAX, Rn );
1.1349 + sh4_x86.tstate = TSTATE_NONE;
1.1350 }
1.1351 }
1.1352 break;
1.1353 @@ -2679,6 +2865,7 @@
1.1354 FADDP_st(1);
1.1355 pop_dr(R_EDX, FRn);
1.1356 JMP_TARGET(end);
1.1357 + sh4_x86.tstate = TSTATE_NONE;
1.1358 }
1.1359 break;
1.1360 case 0x1:
1.1361 @@ -2700,6 +2887,7 @@
1.1362 FSUBP_st(1);
1.1363 pop_dr(R_EDX, FRn);
1.1364 JMP_TARGET(end);
1.1365 + sh4_x86.tstate = TSTATE_NONE;
1.1366 }
1.1367 break;
1.1368 case 0x2:
1.1369 @@ -2721,6 +2909,7 @@
1.1370 FMULP_st(1);
1.1371 pop_dr(R_EDX, FRn);
1.1372 JMP_TARGET(end);
1.1373 + sh4_x86.tstate = TSTATE_NONE;
1.1374 }
1.1375 break;
1.1376 case 0x3:
1.1377 @@ -2742,6 +2931,7 @@
1.1378 FDIVP_st(1);
1.1379 pop_dr(R_EDX, FRn);
1.1380 JMP_TARGET(end);
1.1381 + sh4_x86.tstate = TSTATE_NONE;
1.1382 }
1.1383 break;
1.1384 case 0x4:
1.1385 @@ -2762,6 +2952,7 @@
1.1386 FCOMIP_st(1);
1.1387 SETE_t();
1.1388 FPOP_st();
1.1389 + sh4_x86.tstate = TSTATE_NONE;
1.1390 }
1.1391 break;
1.1392 case 0x5:
1.1393 @@ -2782,6 +2973,7 @@
1.1394 FCOMIP_st(1);
1.1395 SETA_t();
1.1396 FPOP_st();
1.1397 + sh4_x86.tstate = TSTATE_NONE;
1.1398 }
1.1399 break;
1.1400 case 0x6:
1.1401 @@ -2816,6 +3008,7 @@
1.1402 store_fr( R_EDX, R_ECX, FRn|0x01 );
1.1403 JMP_TARGET(end);
1.1404 }
1.1405 + sh4_x86.tstate = TSTATE_NONE;
1.1406 }
1.1407 break;
1.1408 case 0x7:
1.1409 @@ -2849,6 +3042,7 @@
1.1410 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
1.1411 JMP_TARGET(end);
1.1412 }
1.1413 + sh4_x86.tstate = TSTATE_NONE;
1.1414 }
1.1415 break;
1.1416 case 0x8:
1.1417 @@ -2882,6 +3076,7 @@
1.1418 store_fr( R_EDX, R_ECX, FRn|0x01 );
1.1419 JMP_TARGET(end);
1.1420 }
1.1421 + sh4_x86.tstate = TSTATE_NONE;
1.1422 }
1.1423 break;
1.1424 case 0x9:
1.1425 @@ -2921,6 +3116,7 @@
1.1426 store_fr( R_EDX, R_ECX, FRn|0x01 );
1.1427 JMP_TARGET(end);
1.1428 }
1.1429 + sh4_x86.tstate = TSTATE_NONE;
1.1430 }
1.1431 break;
1.1432 case 0xA:
1.1433 @@ -2953,6 +3149,7 @@
1.1434 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
1.1435 JMP_TARGET(end);
1.1436 }
1.1437 + sh4_x86.tstate = TSTATE_NONE;
1.1438 }
1.1439 break;
1.1440 case 0xB:
1.1441 @@ -2991,6 +3188,7 @@
1.1442 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
1.1443 JMP_TARGET(end);
1.1444 }
1.1445 + sh4_x86.tstate = TSTATE_NONE;
1.1446 }
1.1447 break;
1.1448 case 0xC:
1.1449 @@ -3043,6 +3241,7 @@
1.1450 JMP_TARGET(end);
1.1451 }
1.1452 }
1.1453 + sh4_x86.tstate = TSTATE_NONE;
1.1454 }
1.1455 break;
1.1456 case 0xD:
1.1457 @@ -3054,6 +3253,7 @@
1.1458 load_fr_bank( R_ECX );
1.1459 load_spreg( R_EAX, R_FPUL );
1.1460 store_fr( R_ECX, R_EAX, FRn );
1.1461 + sh4_x86.tstate = TSTATE_NONE;
1.1462 }
1.1463 break;
1.1464 case 0x1:
1.1465 @@ -3063,6 +3263,7 @@
1.1466 load_fr_bank( R_ECX );
1.1467 load_fr( R_ECX, R_EAX, FRm );
1.1468 store_spreg( R_EAX, R_FPUL );
1.1469 + sh4_x86.tstate = TSTATE_NONE;
1.1470 }
1.1471 break;
1.1472 case 0x2:
1.1473 @@ -3079,6 +3280,7 @@
1.1474 JMP_TARGET(doubleprec);
1.1475 pop_dr( R_EDX, FRn );
1.1476 JMP_TARGET(end);
1.1477 + sh4_x86.tstate = TSTATE_NONE;
1.1478 }
1.1479 break;
1.1480 case 0x3:
1.1481 @@ -3116,6 +3318,7 @@
1.1482 store_spreg( R_ECX, R_FPUL );
1.1483 FPOP_st();
1.1484 JMP_TARGET(end);
1.1485 + sh4_x86.tstate = TSTATE_NONE;
1.1486 }
1.1487 break;
1.1488 case 0x4:
1.1489 @@ -3135,6 +3338,7 @@
1.1490 FCHS_st0();
1.1491 pop_dr(R_EDX, FRn);
1.1492 JMP_TARGET(end);
1.1493 + sh4_x86.tstate = TSTATE_NONE;
1.1494 }
1.1495 break;
1.1496 case 0x5:
1.1497 @@ -3154,6 +3358,7 @@
1.1498 FABS_st0();
1.1499 pop_dr(R_EDX, FRn);
1.1500 JMP_TARGET(end);
1.1501 + sh4_x86.tstate = TSTATE_NONE;
1.1502 }
1.1503 break;
1.1504 case 0x6:
1.1505 @@ -3173,6 +3378,7 @@
1.1506 FSQRT_st0();
1.1507 pop_dr(R_EDX, FRn);
1.1508 JMP_TARGET(end);
1.1509 + sh4_x86.tstate = TSTATE_NONE;
1.1510 }
1.1511 break;
1.1512 case 0x7:
1.1513 @@ -3189,6 +3395,7 @@
1.1514 FDIVP_st(1);
1.1515 pop_fr(R_EDX, FRn);
1.1516 JMP_TARGET(end);
1.1517 + sh4_x86.tstate = TSTATE_NONE;
1.1518 }
1.1519 break;
1.1520 case 0x8:
1.1521 @@ -3203,6 +3410,7 @@
1.1522 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.1523 store_fr( R_ECX, R_EAX, FRn );
1.1524 JMP_TARGET(end);
1.1525 + sh4_x86.tstate = TSTATE_NONE;
1.1526 }
1.1527 break;
1.1528 case 0x9:
1.1529 @@ -3217,6 +3425,7 @@
1.1530 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.1531 store_fr( R_ECX, R_EAX, FRn );
1.1532 JMP_TARGET(end);
1.1533 + sh4_x86.tstate = TSTATE_NONE;
1.1534 }
1.1535 break;
1.1536 case 0xA:
1.1537 @@ -3230,6 +3439,7 @@
1.1538 push_fpul();
1.1539 pop_dr( R_ECX, FRn );
1.1540 JMP_TARGET(end);
1.1541 + sh4_x86.tstate = TSTATE_NONE;
1.1542 }
1.1543 break;
1.1544 case 0xB:
1.1545 @@ -3243,6 +3453,7 @@
1.1546 push_dr( R_ECX, FRm );
1.1547 pop_fpul();
1.1548 JMP_TARGET(end);
1.1549 + sh4_x86.tstate = TSTATE_NONE;
1.1550 }
1.1551 break;
1.1552 case 0xE:
1.1553 @@ -3271,6 +3482,7 @@
1.1554 FADDP_st(1);
1.1555 pop_fr( R_ECX, (FVn<<2)+3);
1.1556 JMP_TARGET(doubleprec);
1.1557 + sh4_x86.tstate = TSTATE_NONE;
1.1558 }
1.1559 break;
1.1560 case 0xF:
1.1561 @@ -3287,6 +3499,7 @@
1.1562 load_spreg( R_EDX, R_FPUL );
1.1563 call_func2( sh4_fsca, R_EDX, R_ECX );
1.1564 JMP_TARGET(doubleprec);
1.1565 + sh4_x86.tstate = TSTATE_NONE;
1.1566 }
1.1567 break;
1.1568 case 0x1:
1.1569 @@ -3303,6 +3516,7 @@
1.1570 load_xf_bank( R_ECX ); // 12
1.1571 call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
1.1572 JMP_TARGET(doubleprec);
1.1573 + sh4_x86.tstate = TSTATE_NONE;
1.1574 }
1.1575 break;
1.1576 case 0x1:
1.1577 @@ -3313,6 +3527,7 @@
1.1578 load_spreg( R_ECX, R_FPSCR );
1.1579 XOR_imm32_r32( FPSCR_SZ, R_ECX );
1.1580 store_spreg( R_ECX, R_FPSCR );
1.1581 + sh4_x86.tstate = TSTATE_NONE;
1.1582 }
1.1583 break;
1.1584 case 0x2:
1.1585 @@ -3322,6 +3537,7 @@
1.1586 XOR_imm32_r32( FPSCR_FR, R_ECX );
1.1587 store_spreg( R_ECX, R_FPSCR );
1.1588 update_fr_bank( R_ECX );
1.1589 + sh4_x86.tstate = TSTATE_NONE;
1.1590 }
1.1591 break;
1.1592 case 0x3:
1.1593 @@ -3372,6 +3588,7 @@
1.1594 FADDP_st(1);
1.1595 pop_dr( R_EDX, FRn );
1.1596 JMP_TARGET(end);
1.1597 + sh4_x86.tstate = TSTATE_NONE;
1.1598 }
1.1599 break;
1.1600 default:
.