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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 417:bd927df302a9
prev416:714df603c869
next502:c4ecae2b1b5e
author nkeynes
date Thu Oct 04 08:47:27 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Suppress redundant T flag loads
Tweak run_slice for performance
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Wed Oct 03 12:19:03 2007 +0000
1.2 +++ b/src/sh4/sh4x86.in Thu Oct 04 08:47:27 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4x86.in,v 1.18 2007-10-03 12:19:03 nkeynes Exp $
1.6 + * $Id: sh4x86.in,v 1.19 2007-10-04 08:47:27 nkeynes Exp $
1.7 *
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -25,6 +25,7 @@
1.11 #define DEBUG_JUMPS 1
1.12 #endif
1.13
1.14 +#include "sh4/xltcache.h"
1.15 #include "sh4/sh4core.h"
1.16 #include "sh4/sh4trans.h"
1.17 #include "sh4/sh4mmio.h"
1.18 @@ -44,6 +45,7 @@
1.19 gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
1.20 gboolean branch_taken; /* true if we branched unconditionally */
1.21 uint32_t block_start_pc;
1.22 + int tstate;
1.23
1.24 /* Allocated memory for the (block-wide) back-patch list */
1.25 uint32_t **backpatch_list;
1.26 @@ -51,6 +53,28 @@
1.27 uint32_t backpatch_size;
1.28 };
1.29
1.30 +#define TSTATE_NONE -1
1.31 +#define TSTATE_O 0
1.32 +#define TSTATE_C 2
1.33 +#define TSTATE_E 4
1.34 +#define TSTATE_NE 5
1.35 +#define TSTATE_G 0xF
1.36 +#define TSTATE_GE 0xD
1.37 +#define TSTATE_A 7
1.38 +#define TSTATE_AE 3
1.39 +
1.40 +/** Branch if T is set (either in the current cflags, or in sh4r.t) */
1.41 +#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
1.42 + CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
1.43 + OP(0x70+sh4_x86.tstate); OP(rel8); \
1.44 + MARK_JMP(rel8,label)
1.45 +/** Branch if T is clear (either in the current cflags or in sh4r.t) */
1.46 +#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
1.47 + CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
1.48 + OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
1.49 + MARK_JMP(rel8, label)
1.50 +
1.51 +
1.52 #define EXIT_DATA_ADDR_READ 0
1.53 #define EXIT_DATA_ADDR_WRITE 7
1.54 #define EXIT_ILLEGAL 14
1.55 @@ -403,6 +427,7 @@
1.56 sh4_x86.branch_taken = FALSE;
1.57 sh4_x86.backpatch_posn = 0;
1.58 sh4_x86.block_start_pc = pc;
1.59 + sh4_x86.tstate = TSTATE_NONE;
1.60 }
1.61
1.62 /**
1.63 @@ -427,9 +452,10 @@
1.64 */
1.65 void exit_block_pcset( pc )
1.66 {
1.67 - XOR_r32_r32( R_EAX, R_EAX ); // 2
1.68 load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
1.69 ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
1.70 + load_spreg( R_EAX, REG_OFFSET(pc) );
1.71 + call_func1(xlat_get_code,R_EAX);
1.72 POP_r32(R_EBP);
1.73 RET();
1.74 }
1.75 @@ -462,20 +488,20 @@
1.76 JMP_TARGET(target3);
1.77 JMP_TARGET(target4);
1.78 JMP_TARGET(target5);
1.79 + // Raise exception
1.80 load_spreg( R_ECX, REG_OFFSET(pc) );
1.81 ADD_r32_r32( R_EDX, R_ECX );
1.82 ADD_r32_r32( R_EDX, R_ECX );
1.83 store_spreg( R_ECX, REG_OFFSET(pc) );
1.84 MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
1.85 - load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
1.86 MUL_r32( R_EDX );
1.87 - ADD_r32_r32( R_EAX, R_ECX );
1.88 - store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
1.89 + ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
1.90
1.91 load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
1.92 CALL_r32( R_EAX ); // 2
1.93 ADD_imm8s_r32( 4, R_ESP );
1.94 - XOR_r32_r32( R_EAX, R_EAX );
1.95 + load_spreg( R_EAX, REG_OFFSET(pc) );
1.96 + call_func1(xlat_get_code,R_EAX);
1.97 POP_r32(R_EBP);
1.98 RET();
1.99
1.100 @@ -524,19 +550,24 @@
1.101 load_reg( R_ECX, Rn );
1.102 ADD_r32_r32( R_EAX, R_ECX );
1.103 store_reg( R_ECX, Rn );
1.104 + sh4_x86.tstate = TSTATE_NONE;
1.105 :}
1.106 ADD #imm, Rn {:
1.107 load_reg( R_EAX, Rn );
1.108 ADD_imm8s_r32( imm, R_EAX );
1.109 store_reg( R_EAX, Rn );
1.110 + sh4_x86.tstate = TSTATE_NONE;
1.111 :}
1.112 ADDC Rm, Rn {:
1.113 + if( sh4_x86.tstate != TSTATE_C ) {
1.114 + LDC_t();
1.115 + }
1.116 load_reg( R_EAX, Rm );
1.117 load_reg( R_ECX, Rn );
1.118 - LDC_t();
1.119 ADC_r32_r32( R_EAX, R_ECX );
1.120 store_reg( R_ECX, Rn );
1.121 SETC_t();
1.122 + sh4_x86.tstate = TSTATE_C;
1.123 :}
1.124 ADDV Rm, Rn {:
1.125 load_reg( R_EAX, Rm );
1.126 @@ -544,17 +575,20 @@
1.127 ADD_r32_r32( R_EAX, R_ECX );
1.128 store_reg( R_ECX, Rn );
1.129 SETO_t();
1.130 + sh4_x86.tstate = TSTATE_O;
1.131 :}
1.132 AND Rm, Rn {:
1.133 load_reg( R_EAX, Rm );
1.134 load_reg( R_ECX, Rn );
1.135 AND_r32_r32( R_EAX, R_ECX );
1.136 store_reg( R_ECX, Rn );
1.137 + sh4_x86.tstate = TSTATE_NONE;
1.138 :}
1.139 AND #imm, R0 {:
1.140 load_reg( R_EAX, 0 );
1.141 AND_imm32_r32(imm, R_EAX);
1.142 store_reg( R_EAX, 0 );
1.143 + sh4_x86.tstate = TSTATE_NONE;
1.144 :}
1.145 AND.B #imm, @(R0, GBR) {:
1.146 load_reg( R_EAX, 0 );
1.147 @@ -565,51 +599,60 @@
1.148 POP_r32(R_ECX);
1.149 AND_imm32_r32(imm, R_EAX );
1.150 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.151 + sh4_x86.tstate = TSTATE_NONE;
1.152 :}
1.153 CMP/EQ Rm, Rn {:
1.154 load_reg( R_EAX, Rm );
1.155 load_reg( R_ECX, Rn );
1.156 CMP_r32_r32( R_EAX, R_ECX );
1.157 SETE_t();
1.158 + sh4_x86.tstate = TSTATE_E;
1.159 :}
1.160 CMP/EQ #imm, R0 {:
1.161 load_reg( R_EAX, 0 );
1.162 CMP_imm8s_r32(imm, R_EAX);
1.163 SETE_t();
1.164 + sh4_x86.tstate = TSTATE_E;
1.165 :}
1.166 CMP/GE Rm, Rn {:
1.167 load_reg( R_EAX, Rm );
1.168 load_reg( R_ECX, Rn );
1.169 CMP_r32_r32( R_EAX, R_ECX );
1.170 SETGE_t();
1.171 + sh4_x86.tstate = TSTATE_GE;
1.172 :}
1.173 CMP/GT Rm, Rn {:
1.174 load_reg( R_EAX, Rm );
1.175 load_reg( R_ECX, Rn );
1.176 CMP_r32_r32( R_EAX, R_ECX );
1.177 SETG_t();
1.178 + sh4_x86.tstate = TSTATE_G;
1.179 :}
1.180 CMP/HI Rm, Rn {:
1.181 load_reg( R_EAX, Rm );
1.182 load_reg( R_ECX, Rn );
1.183 CMP_r32_r32( R_EAX, R_ECX );
1.184 SETA_t();
1.185 + sh4_x86.tstate = TSTATE_A;
1.186 :}
1.187 CMP/HS Rm, Rn {:
1.188 load_reg( R_EAX, Rm );
1.189 load_reg( R_ECX, Rn );
1.190 CMP_r32_r32( R_EAX, R_ECX );
1.191 SETAE_t();
1.192 + sh4_x86.tstate = TSTATE_AE;
1.193 :}
1.194 CMP/PL Rn {:
1.195 load_reg( R_EAX, Rn );
1.196 CMP_imm8s_r32( 0, R_EAX );
1.197 SETG_t();
1.198 + sh4_x86.tstate = TSTATE_G;
1.199 :}
1.200 CMP/PZ Rn {:
1.201 load_reg( R_EAX, Rn );
1.202 CMP_imm8s_r32( 0, R_EAX );
1.203 SETGE_t();
1.204 + sh4_x86.tstate = TSTATE_GE;
1.205 :}
1.206 CMP/STR Rm, Rn {:
1.207 load_reg( R_EAX, Rm );
1.208 @@ -627,6 +670,7 @@
1.209 JMP_TARGET(target2);
1.210 JMP_TARGET(target3);
1.211 SETE_t();
1.212 + sh4_x86.tstate = TSTATE_E;
1.213 :}
1.214 DIV0S Rm, Rn {:
1.215 load_reg( R_EAX, Rm );
1.216 @@ -637,17 +681,21 @@
1.217 store_spreg( R_ECX, R_Q );
1.218 CMP_r32_r32( R_EAX, R_ECX );
1.219 SETNE_t();
1.220 + sh4_x86.tstate = TSTATE_NE;
1.221 :}
1.222 DIV0U {:
1.223 XOR_r32_r32( R_EAX, R_EAX );
1.224 store_spreg( R_EAX, R_Q );
1.225 store_spreg( R_EAX, R_M );
1.226 store_spreg( R_EAX, R_T );
1.227 + sh4_x86.tstate = TSTATE_C; // works for DIV1
1.228 :}
1.229 DIV1 Rm, Rn {:
1.230 load_spreg( R_ECX, R_M );
1.231 load_reg( R_EAX, Rn );
1.232 - LDC_t();
1.233 + if( sh4_x86.tstate != TSTATE_C ) {
1.234 + LDC_t();
1.235 + }
1.236 RCL1_r32( R_EAX );
1.237 SETC_r8( R_DL ); // Q'
1.238 CMP_sh4r_r32( R_Q, R_ECX );
1.239 @@ -665,6 +713,7 @@
1.240 XOR_imm8s_r32( 1, R_AL ); // T = !Q'
1.241 MOVZX_r8_r32( R_AL, R_EAX );
1.242 store_spreg( R_EAX, R_T );
1.243 + sh4_x86.tstate = TSTATE_NONE;
1.244 :}
1.245 DMULS.L Rm, Rn {:
1.246 load_reg( R_EAX, Rm );
1.247 @@ -672,6 +721,7 @@
1.248 IMUL_r32(R_ECX);
1.249 store_spreg( R_EDX, R_MACH );
1.250 store_spreg( R_EAX, R_MACL );
1.251 + sh4_x86.tstate = TSTATE_NONE;
1.252 :}
1.253 DMULU.L Rm, Rn {:
1.254 load_reg( R_EAX, Rm );
1.255 @@ -679,12 +729,14 @@
1.256 MUL_r32(R_ECX);
1.257 store_spreg( R_EDX, R_MACH );
1.258 store_spreg( R_EAX, R_MACL );
1.259 + sh4_x86.tstate = TSTATE_NONE;
1.260 :}
1.261 DT Rn {:
1.262 load_reg( R_EAX, Rn );
1.263 ADD_imm8s_r32( -1, R_EAX );
1.264 store_reg( R_EAX, Rn );
1.265 SETE_t();
1.266 + sh4_x86.tstate = TSTATE_E;
1.267 :}
1.268 EXTS.B Rm, Rn {:
1.269 load_reg( R_EAX, Rm );
1.270 @@ -728,6 +780,7 @@
1.271 JE_rel8( 7, nosat );
1.272 call_func0( signsat48 );
1.273 JMP_TARGET( nosat );
1.274 + sh4_x86.tstate = TSTATE_NONE;
1.275 :}
1.276 MAC.W @Rm+, @Rn+ {:
1.277 load_reg( R_ECX, Rm );
1.278 @@ -768,6 +821,7 @@
1.279 JMP_TARGET(end);
1.280 JMP_TARGET(end2);
1.281 JMP_TARGET(end3);
1.282 + sh4_x86.tstate = TSTATE_NONE;
1.283 :}
1.284 MOVT Rn {:
1.285 load_spreg( R_EAX, R_T );
1.286 @@ -778,23 +832,27 @@
1.287 load_reg( R_ECX, Rn );
1.288 MUL_r32( R_ECX );
1.289 store_spreg( R_EAX, R_MACL );
1.290 + sh4_x86.tstate = TSTATE_NONE;
1.291 :}
1.292 MULS.W Rm, Rn {:
1.293 load_reg16s( R_EAX, Rm );
1.294 load_reg16s( R_ECX, Rn );
1.295 MUL_r32( R_ECX );
1.296 store_spreg( R_EAX, R_MACL );
1.297 + sh4_x86.tstate = TSTATE_NONE;
1.298 :}
1.299 MULU.W Rm, Rn {:
1.300 load_reg16u( R_EAX, Rm );
1.301 load_reg16u( R_ECX, Rn );
1.302 MUL_r32( R_ECX );
1.303 store_spreg( R_EAX, R_MACL );
1.304 + sh4_x86.tstate = TSTATE_NONE;
1.305 :}
1.306 NEG Rm, Rn {:
1.307 load_reg( R_EAX, Rm );
1.308 NEG_r32( R_EAX );
1.309 store_reg( R_EAX, Rn );
1.310 + sh4_x86.tstate = TSTATE_NONE;
1.311 :}
1.312 NEGC Rm, Rn {:
1.313 load_reg( R_EAX, Rm );
1.314 @@ -803,22 +861,26 @@
1.315 SBB_r32_r32( R_EAX, R_ECX );
1.316 store_reg( R_ECX, Rn );
1.317 SETC_t();
1.318 + sh4_x86.tstate = TSTATE_C;
1.319 :}
1.320 NOT Rm, Rn {:
1.321 load_reg( R_EAX, Rm );
1.322 NOT_r32( R_EAX );
1.323 store_reg( R_EAX, Rn );
1.324 + sh4_x86.tstate = TSTATE_NONE;
1.325 :}
1.326 OR Rm, Rn {:
1.327 load_reg( R_EAX, Rm );
1.328 load_reg( R_ECX, Rn );
1.329 OR_r32_r32( R_EAX, R_ECX );
1.330 store_reg( R_ECX, Rn );
1.331 + sh4_x86.tstate = TSTATE_NONE;
1.332 :}
1.333 OR #imm, R0 {:
1.334 load_reg( R_EAX, 0 );
1.335 OR_imm32_r32(imm, R_EAX);
1.336 store_reg( R_EAX, 0 );
1.337 + sh4_x86.tstate = TSTATE_NONE;
1.338 :}
1.339 OR.B #imm, @(R0, GBR) {:
1.340 load_reg( R_EAX, 0 );
1.341 @@ -829,32 +891,41 @@
1.342 POP_r32(R_ECX);
1.343 OR_imm32_r32(imm, R_EAX );
1.344 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.345 + sh4_x86.tstate = TSTATE_NONE;
1.346 :}
1.347 ROTCL Rn {:
1.348 load_reg( R_EAX, Rn );
1.349 - LDC_t();
1.350 + if( sh4_x86.tstate != TSTATE_C ) {
1.351 + LDC_t();
1.352 + }
1.353 RCL1_r32( R_EAX );
1.354 store_reg( R_EAX, Rn );
1.355 SETC_t();
1.356 + sh4_x86.tstate = TSTATE_C;
1.357 :}
1.358 ROTCR Rn {:
1.359 load_reg( R_EAX, Rn );
1.360 - LDC_t();
1.361 + if( sh4_x86.tstate != TSTATE_C ) {
1.362 + LDC_t();
1.363 + }
1.364 RCR1_r32( R_EAX );
1.365 store_reg( R_EAX, Rn );
1.366 SETC_t();
1.367 + sh4_x86.tstate = TSTATE_C;
1.368 :}
1.369 ROTL Rn {:
1.370 load_reg( R_EAX, Rn );
1.371 ROL1_r32( R_EAX );
1.372 store_reg( R_EAX, Rn );
1.373 SETC_t();
1.374 + sh4_x86.tstate = TSTATE_C;
1.375 :}
1.376 ROTR Rn {:
1.377 load_reg( R_EAX, Rn );
1.378 ROR1_r32( R_EAX );
1.379 store_reg( R_EAX, Rn );
1.380 SETC_t();
1.381 + sh4_x86.tstate = TSTATE_C;
1.382 :}
1.383 SHAD Rm, Rn {:
1.384 /* Annoyingly enough, not directly convertible */
1.385 @@ -879,6 +950,7 @@
1.386 JMP_TARGET(end);
1.387 JMP_TARGET(end2);
1.388 store_reg( R_EAX, Rn );
1.389 + sh4_x86.tstate = TSTATE_NONE;
1.390 :}
1.391 SHLD Rm, Rn {:
1.392 load_reg( R_EAX, Rn );
1.393 @@ -902,74 +974,89 @@
1.394 JMP_TARGET(end);
1.395 JMP_TARGET(end2);
1.396 store_reg( R_EAX, Rn );
1.397 + sh4_x86.tstate = TSTATE_NONE;
1.398 :}
1.399 SHAL Rn {:
1.400 load_reg( R_EAX, Rn );
1.401 SHL1_r32( R_EAX );
1.402 SETC_t();
1.403 store_reg( R_EAX, Rn );
1.404 + sh4_x86.tstate = TSTATE_C;
1.405 :}
1.406 SHAR Rn {:
1.407 load_reg( R_EAX, Rn );
1.408 SAR1_r32( R_EAX );
1.409 SETC_t();
1.410 store_reg( R_EAX, Rn );
1.411 + sh4_x86.tstate = TSTATE_C;
1.412 :}
1.413 SHLL Rn {:
1.414 load_reg( R_EAX, Rn );
1.415 SHL1_r32( R_EAX );
1.416 SETC_t();
1.417 store_reg( R_EAX, Rn );
1.418 + sh4_x86.tstate = TSTATE_C;
1.419 :}
1.420 SHLL2 Rn {:
1.421 load_reg( R_EAX, Rn );
1.422 SHL_imm8_r32( 2, R_EAX );
1.423 store_reg( R_EAX, Rn );
1.424 + sh4_x86.tstate = TSTATE_NONE;
1.425 :}
1.426 SHLL8 Rn {:
1.427 load_reg( R_EAX, Rn );
1.428 SHL_imm8_r32( 8, R_EAX );
1.429 store_reg( R_EAX, Rn );
1.430 + sh4_x86.tstate = TSTATE_NONE;
1.431 :}
1.432 SHLL16 Rn {:
1.433 load_reg( R_EAX, Rn );
1.434 SHL_imm8_r32( 16, R_EAX );
1.435 store_reg( R_EAX, Rn );
1.436 + sh4_x86.tstate = TSTATE_NONE;
1.437 :}
1.438 SHLR Rn {:
1.439 load_reg( R_EAX, Rn );
1.440 SHR1_r32( R_EAX );
1.441 SETC_t();
1.442 store_reg( R_EAX, Rn );
1.443 + sh4_x86.tstate = TSTATE_C;
1.444 :}
1.445 SHLR2 Rn {:
1.446 load_reg( R_EAX, Rn );
1.447 SHR_imm8_r32( 2, R_EAX );
1.448 store_reg( R_EAX, Rn );
1.449 + sh4_x86.tstate = TSTATE_NONE;
1.450 :}
1.451 SHLR8 Rn {:
1.452 load_reg( R_EAX, Rn );
1.453 SHR_imm8_r32( 8, R_EAX );
1.454 store_reg( R_EAX, Rn );
1.455 + sh4_x86.tstate = TSTATE_NONE;
1.456 :}
1.457 SHLR16 Rn {:
1.458 load_reg( R_EAX, Rn );
1.459 SHR_imm8_r32( 16, R_EAX );
1.460 store_reg( R_EAX, Rn );
1.461 + sh4_x86.tstate = TSTATE_NONE;
1.462 :}
1.463 SUB Rm, Rn {:
1.464 load_reg( R_EAX, Rm );
1.465 load_reg( R_ECX, Rn );
1.466 SUB_r32_r32( R_EAX, R_ECX );
1.467 store_reg( R_ECX, Rn );
1.468 + sh4_x86.tstate = TSTATE_NONE;
1.469 :}
1.470 SUBC Rm, Rn {:
1.471 load_reg( R_EAX, Rm );
1.472 load_reg( R_ECX, Rn );
1.473 - LDC_t();
1.474 + if( sh4_x86.tstate != TSTATE_C ) {
1.475 + LDC_t();
1.476 + }
1.477 SBB_r32_r32( R_EAX, R_ECX );
1.478 store_reg( R_ECX, Rn );
1.479 SETC_t();
1.480 + sh4_x86.tstate = TSTATE_C;
1.481 :}
1.482 SUBV Rm, Rn {:
1.483 load_reg( R_EAX, Rm );
1.484 @@ -977,6 +1064,7 @@
1.485 SUB_r32_r32( R_EAX, R_ECX );
1.486 store_reg( R_ECX, Rn );
1.487 SETO_t();
1.488 + sh4_x86.tstate = TSTATE_O;
1.489 :}
1.490 SWAP.B Rm, Rn {:
1.491 load_reg( R_EAX, Rm );
1.492 @@ -990,6 +1078,7 @@
1.493 SHR_imm8_r32( 16, R_EAX );
1.494 OR_r32_r32( R_EAX, R_ECX );
1.495 store_reg( R_ECX, Rn );
1.496 + sh4_x86.tstate = TSTATE_NONE;
1.497 :}
1.498 TAS.B @Rn {:
1.499 load_reg( R_ECX, Rn );
1.500 @@ -999,17 +1088,20 @@
1.501 OR_imm8_r8( 0x80, R_AL );
1.502 load_reg( R_ECX, Rn );
1.503 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.504 + sh4_x86.tstate = TSTATE_NONE;
1.505 :}
1.506 TST Rm, Rn {:
1.507 load_reg( R_EAX, Rm );
1.508 load_reg( R_ECX, Rn );
1.509 TEST_r32_r32( R_EAX, R_ECX );
1.510 SETE_t();
1.511 + sh4_x86.tstate = TSTATE_E;
1.512 :}
1.513 TST #imm, R0 {:
1.514 load_reg( R_EAX, 0 );
1.515 TEST_imm32_r32( imm, R_EAX );
1.516 SETE_t();
1.517 + sh4_x86.tstate = TSTATE_E;
1.518 :}
1.519 TST.B #imm, @(R0, GBR) {:
1.520 load_reg( R_EAX, 0);
1.521 @@ -1018,17 +1110,20 @@
1.522 MEM_READ_BYTE( R_ECX, R_EAX );
1.523 TEST_imm8_r8( imm, R_AL );
1.524 SETE_t();
1.525 + sh4_x86.tstate = TSTATE_E;
1.526 :}
1.527 XOR Rm, Rn {:
1.528 load_reg( R_EAX, Rm );
1.529 load_reg( R_ECX, Rn );
1.530 XOR_r32_r32( R_EAX, R_ECX );
1.531 store_reg( R_ECX, Rn );
1.532 + sh4_x86.tstate = TSTATE_NONE;
1.533 :}
1.534 XOR #imm, R0 {:
1.535 load_reg( R_EAX, 0 );
1.536 XOR_imm32_r32( imm, R_EAX );
1.537 store_reg( R_EAX, 0 );
1.538 + sh4_x86.tstate = TSTATE_NONE;
1.539 :}
1.540 XOR.B #imm, @(R0, GBR) {:
1.541 load_reg( R_EAX, 0 );
1.542 @@ -1039,6 +1134,7 @@
1.543 POP_r32(R_ECX);
1.544 XOR_imm32_r32( imm, R_EAX );
1.545 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.546 + sh4_x86.tstate = TSTATE_NONE;
1.547 :}
1.548 XTRCT Rm, Rn {:
1.549 load_reg( R_EAX, Rm );
1.550 @@ -1047,6 +1143,7 @@
1.551 SHR_imm8_r32( 16, R_ECX );
1.552 OR_r32_r32( R_EAX, R_ECX );
1.553 store_reg( R_ECX, Rn );
1.554 + sh4_x86.tstate = TSTATE_NONE;
1.555 :}
1.556
1.557 /* Data move instructions */
1.558 @@ -1062,6 +1159,7 @@
1.559 load_reg( R_EAX, Rm );
1.560 load_reg( R_ECX, Rn );
1.561 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.562 + sh4_x86.tstate = TSTATE_NONE;
1.563 :}
1.564 MOV.B Rm, @-Rn {:
1.565 load_reg( R_EAX, Rm );
1.566 @@ -1069,6 +1167,7 @@
1.567 ADD_imm8s_r32( -1, R_ECX );
1.568 store_reg( R_ECX, Rn );
1.569 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.570 + sh4_x86.tstate = TSTATE_NONE;
1.571 :}
1.572 MOV.B Rm, @(R0, Rn) {:
1.573 load_reg( R_EAX, 0 );
1.574 @@ -1076,23 +1175,27 @@
1.575 ADD_r32_r32( R_EAX, R_ECX );
1.576 load_reg( R_EAX, Rm );
1.577 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.578 + sh4_x86.tstate = TSTATE_NONE;
1.579 :}
1.580 MOV.B R0, @(disp, GBR) {:
1.581 load_reg( R_EAX, 0 );
1.582 load_spreg( R_ECX, R_GBR );
1.583 ADD_imm32_r32( disp, R_ECX );
1.584 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.585 + sh4_x86.tstate = TSTATE_NONE;
1.586 :}
1.587 MOV.B R0, @(disp, Rn) {:
1.588 load_reg( R_EAX, 0 );
1.589 load_reg( R_ECX, Rn );
1.590 ADD_imm32_r32( disp, R_ECX );
1.591 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.592 + sh4_x86.tstate = TSTATE_NONE;
1.593 :}
1.594 MOV.B @Rm, Rn {:
1.595 load_reg( R_ECX, Rm );
1.596 MEM_READ_BYTE( R_ECX, R_EAX );
1.597 store_reg( R_EAX, Rn );
1.598 + sh4_x86.tstate = TSTATE_NONE;
1.599 :}
1.600 MOV.B @Rm+, Rn {:
1.601 load_reg( R_ECX, Rm );
1.602 @@ -1101,6 +1204,7 @@
1.603 store_reg( R_EAX, Rm );
1.604 MEM_READ_BYTE( R_ECX, R_EAX );
1.605 store_reg( R_EAX, Rn );
1.606 + sh4_x86.tstate = TSTATE_NONE;
1.607 :}
1.608 MOV.B @(R0, Rm), Rn {:
1.609 load_reg( R_EAX, 0 );
1.610 @@ -1108,18 +1212,21 @@
1.611 ADD_r32_r32( R_EAX, R_ECX );
1.612 MEM_READ_BYTE( R_ECX, R_EAX );
1.613 store_reg( R_EAX, Rn );
1.614 + sh4_x86.tstate = TSTATE_NONE;
1.615 :}
1.616 MOV.B @(disp, GBR), R0 {:
1.617 load_spreg( R_ECX, R_GBR );
1.618 ADD_imm32_r32( disp, R_ECX );
1.619 MEM_READ_BYTE( R_ECX, R_EAX );
1.620 store_reg( R_EAX, 0 );
1.621 + sh4_x86.tstate = TSTATE_NONE;
1.622 :}
1.623 MOV.B @(disp, Rm), R0 {:
1.624 load_reg( R_ECX, Rm );
1.625 ADD_imm32_r32( disp, R_ECX );
1.626 MEM_READ_BYTE( R_ECX, R_EAX );
1.627 store_reg( R_EAX, 0 );
1.628 + sh4_x86.tstate = TSTATE_NONE;
1.629 :}
1.630 MOV.L Rm, @Rn {:
1.631 load_reg( R_EAX, Rm );
1.632 @@ -1127,6 +1234,7 @@
1.633 precheck();
1.634 check_walign32(R_ECX);
1.635 MEM_WRITE_LONG( R_ECX, R_EAX );
1.636 + sh4_x86.tstate = TSTATE_NONE;
1.637 :}
1.638 MOV.L Rm, @-Rn {:
1.639 load_reg( R_EAX, Rm );
1.640 @@ -1136,6 +1244,7 @@
1.641 ADD_imm8s_r32( -4, R_ECX );
1.642 store_reg( R_ECX, Rn );
1.643 MEM_WRITE_LONG( R_ECX, R_EAX );
1.644 + sh4_x86.tstate = TSTATE_NONE;
1.645 :}
1.646 MOV.L Rm, @(R0, Rn) {:
1.647 load_reg( R_EAX, 0 );
1.648 @@ -1145,6 +1254,7 @@
1.649 check_walign32( R_ECX );
1.650 load_reg( R_EAX, Rm );
1.651 MEM_WRITE_LONG( R_ECX, R_EAX );
1.652 + sh4_x86.tstate = TSTATE_NONE;
1.653 :}
1.654 MOV.L R0, @(disp, GBR) {:
1.655 load_spreg( R_ECX, R_GBR );
1.656 @@ -1153,6 +1263,7 @@
1.657 precheck();
1.658 check_walign32( R_ECX );
1.659 MEM_WRITE_LONG( R_ECX, R_EAX );
1.660 + sh4_x86.tstate = TSTATE_NONE;
1.661 :}
1.662 MOV.L Rm, @(disp, Rn) {:
1.663 load_reg( R_ECX, Rn );
1.664 @@ -1161,6 +1272,7 @@
1.665 precheck();
1.666 check_walign32( R_ECX );
1.667 MEM_WRITE_LONG( R_ECX, R_EAX );
1.668 + sh4_x86.tstate = TSTATE_NONE;
1.669 :}
1.670 MOV.L @Rm, Rn {:
1.671 load_reg( R_ECX, Rm );
1.672 @@ -1168,6 +1280,7 @@
1.673 check_ralign32( R_ECX );
1.674 MEM_READ_LONG( R_ECX, R_EAX );
1.675 store_reg( R_EAX, Rn );
1.676 + sh4_x86.tstate = TSTATE_NONE;
1.677 :}
1.678 MOV.L @Rm+, Rn {:
1.679 load_reg( R_EAX, Rm );
1.680 @@ -1178,6 +1291,7 @@
1.681 store_reg( R_EAX, Rm );
1.682 MEM_READ_LONG( R_ECX, R_EAX );
1.683 store_reg( R_EAX, Rn );
1.684 + sh4_x86.tstate = TSTATE_NONE;
1.685 :}
1.686 MOV.L @(R0, Rm), Rn {:
1.687 load_reg( R_EAX, 0 );
1.688 @@ -1187,6 +1301,7 @@
1.689 check_ralign32( R_ECX );
1.690 MEM_READ_LONG( R_ECX, R_EAX );
1.691 store_reg( R_EAX, Rn );
1.692 + sh4_x86.tstate = TSTATE_NONE;
1.693 :}
1.694 MOV.L @(disp, GBR), R0 {:
1.695 load_spreg( R_ECX, R_GBR );
1.696 @@ -1195,6 +1310,7 @@
1.697 check_ralign32( R_ECX );
1.698 MEM_READ_LONG( R_ECX, R_EAX );
1.699 store_reg( R_EAX, 0 );
1.700 + sh4_x86.tstate = TSTATE_NONE;
1.701 :}
1.702 MOV.L @(disp, PC), Rn {:
1.703 if( sh4_x86.in_delay_slot ) {
1.704 @@ -1209,6 +1325,7 @@
1.705 MEM_READ_LONG( R_ECX, R_EAX );
1.706 }
1.707 store_reg( R_EAX, Rn );
1.708 + sh4_x86.tstate = TSTATE_NONE;
1.709 }
1.710 :}
1.711 MOV.L @(disp, Rm), Rn {:
1.712 @@ -1218,6 +1335,7 @@
1.713 check_ralign32( R_ECX );
1.714 MEM_READ_LONG( R_ECX, R_EAX );
1.715 store_reg( R_EAX, Rn );
1.716 + sh4_x86.tstate = TSTATE_NONE;
1.717 :}
1.718 MOV.W Rm, @Rn {:
1.719 load_reg( R_ECX, Rn );
1.720 @@ -1225,6 +1343,7 @@
1.721 check_walign16( R_ECX );
1.722 load_reg( R_EAX, Rm );
1.723 MEM_WRITE_WORD( R_ECX, R_EAX );
1.724 + sh4_x86.tstate = TSTATE_NONE;
1.725 :}
1.726 MOV.W Rm, @-Rn {:
1.727 load_reg( R_ECX, Rn );
1.728 @@ -1234,6 +1353,7 @@
1.729 ADD_imm8s_r32( -2, R_ECX );
1.730 store_reg( R_ECX, Rn );
1.731 MEM_WRITE_WORD( R_ECX, R_EAX );
1.732 + sh4_x86.tstate = TSTATE_NONE;
1.733 :}
1.734 MOV.W Rm, @(R0, Rn) {:
1.735 load_reg( R_EAX, 0 );
1.736 @@ -1243,6 +1363,7 @@
1.737 check_walign16( R_ECX );
1.738 load_reg( R_EAX, Rm );
1.739 MEM_WRITE_WORD( R_ECX, R_EAX );
1.740 + sh4_x86.tstate = TSTATE_NONE;
1.741 :}
1.742 MOV.W R0, @(disp, GBR) {:
1.743 load_spreg( R_ECX, R_GBR );
1.744 @@ -1251,6 +1372,7 @@
1.745 precheck();
1.746 check_walign16( R_ECX );
1.747 MEM_WRITE_WORD( R_ECX, R_EAX );
1.748 + sh4_x86.tstate = TSTATE_NONE;
1.749 :}
1.750 MOV.W R0, @(disp, Rn) {:
1.751 load_reg( R_ECX, Rn );
1.752 @@ -1259,6 +1381,7 @@
1.753 precheck();
1.754 check_walign16( R_ECX );
1.755 MEM_WRITE_WORD( R_ECX, R_EAX );
1.756 + sh4_x86.tstate = TSTATE_NONE;
1.757 :}
1.758 MOV.W @Rm, Rn {:
1.759 load_reg( R_ECX, Rm );
1.760 @@ -1266,6 +1389,7 @@
1.761 check_ralign16( R_ECX );
1.762 MEM_READ_WORD( R_ECX, R_EAX );
1.763 store_reg( R_EAX, Rn );
1.764 + sh4_x86.tstate = TSTATE_NONE;
1.765 :}
1.766 MOV.W @Rm+, Rn {:
1.767 load_reg( R_EAX, Rm );
1.768 @@ -1276,6 +1400,7 @@
1.769 store_reg( R_EAX, Rm );
1.770 MEM_READ_WORD( R_ECX, R_EAX );
1.771 store_reg( R_EAX, Rn );
1.772 + sh4_x86.tstate = TSTATE_NONE;
1.773 :}
1.774 MOV.W @(R0, Rm), Rn {:
1.775 load_reg( R_EAX, 0 );
1.776 @@ -1285,6 +1410,7 @@
1.777 check_ralign16( R_ECX );
1.778 MEM_READ_WORD( R_ECX, R_EAX );
1.779 store_reg( R_EAX, Rn );
1.780 + sh4_x86.tstate = TSTATE_NONE;
1.781 :}
1.782 MOV.W @(disp, GBR), R0 {:
1.783 load_spreg( R_ECX, R_GBR );
1.784 @@ -1293,6 +1419,7 @@
1.785 check_ralign16( R_ECX );
1.786 MEM_READ_WORD( R_ECX, R_EAX );
1.787 store_reg( R_EAX, 0 );
1.788 + sh4_x86.tstate = TSTATE_NONE;
1.789 :}
1.790 MOV.W @(disp, PC), Rn {:
1.791 if( sh4_x86.in_delay_slot ) {
1.792 @@ -1301,6 +1428,7 @@
1.793 load_imm32( R_ECX, pc + disp + 4 );
1.794 MEM_READ_WORD( R_ECX, R_EAX );
1.795 store_reg( R_EAX, Rn );
1.796 + sh4_x86.tstate = TSTATE_NONE;
1.797 }
1.798 :}
1.799 MOV.W @(disp, Rm), R0 {:
1.800 @@ -1310,6 +1438,7 @@
1.801 check_ralign16( R_ECX );
1.802 MEM_READ_WORD( R_ECX, R_EAX );
1.803 store_reg( R_EAX, 0 );
1.804 + sh4_x86.tstate = TSTATE_NONE;
1.805 :}
1.806 MOVA @(disp, PC), R0 {:
1.807 if( sh4_x86.in_delay_slot ) {
1.808 @@ -1325,6 +1454,7 @@
1.809 precheck();
1.810 check_walign32( R_ECX );
1.811 MEM_WRITE_LONG( R_ECX, R_EAX );
1.812 + sh4_x86.tstate = TSTATE_NONE;
1.813 :}
1.814
1.815 /* Control transfer instructions */
1.816 @@ -1332,8 +1462,7 @@
1.817 if( sh4_x86.in_delay_slot ) {
1.818 SLOTILLEGAL();
1.819 } else {
1.820 - CMP_imm8s_sh4r( 0, R_T );
1.821 - JNE_rel8( 29, nottaken );
1.822 + JT_rel8( 29, nottaken );
1.823 exit_block( disp + pc + 4, pc+2 );
1.824 JMP_TARGET(nottaken);
1.825 return 2;
1.826 @@ -1344,8 +1473,11 @@
1.827 SLOTILLEGAL();
1.828 } else {
1.829 sh4_x86.in_delay_slot = TRUE;
1.830 - CMP_imm8s_sh4r( 0, R_T );
1.831 - OP(0x0F); OP(0x85); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
1.832 + if( sh4_x86.tstate == TSTATE_NONE ) {
1.833 + CMP_imm8s_sh4r( 1, R_T );
1.834 + sh4_x86.tstate = TSTATE_E;
1.835 + }
1.836 + OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
1.837 sh4_x86_translate_instruction(pc+2);
1.838 exit_block( disp + pc + 4, pc+4 );
1.839 // not taken
1.840 @@ -1373,6 +1505,7 @@
1.841 ADD_imm32_r32( pc + 4, R_EAX );
1.842 store_spreg( R_EAX, REG_OFFSET(pc) );
1.843 sh4_x86.in_delay_slot = TRUE;
1.844 + sh4_x86.tstate = TSTATE_NONE;
1.845 sh4_x86_translate_instruction( pc + 2 );
1.846 exit_block_pcset(pc+2);
1.847 sh4_x86.branch_taken = TRUE;
1.848 @@ -1401,6 +1534,7 @@
1.849 ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
1.850 store_spreg( R_ECX, REG_OFFSET(pc) );
1.851 sh4_x86.in_delay_slot = TRUE;
1.852 + sh4_x86.tstate = TSTATE_NONE;
1.853 sh4_x86_translate_instruction( pc + 2 );
1.854 exit_block_pcset(pc+2);
1.855 sh4_x86.branch_taken = TRUE;
1.856 @@ -1411,8 +1545,7 @@
1.857 if( sh4_x86.in_delay_slot ) {
1.858 SLOTILLEGAL();
1.859 } else {
1.860 - CMP_imm8s_sh4r( 0, R_T );
1.861 - JE_rel8( 29, nottaken );
1.862 + JF_rel8( 29, nottaken );
1.863 exit_block( disp + pc + 4, pc+2 );
1.864 JMP_TARGET(nottaken);
1.865 return 2;
1.866 @@ -1423,8 +1556,11 @@
1.867 SLOTILLEGAL();
1.868 } else {
1.869 sh4_x86.in_delay_slot = TRUE;
1.870 - CMP_imm8s_sh4r( 0, R_T );
1.871 - OP(0x0F); OP(0x84); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
1.872 + if( sh4_x86.tstate == TSTATE_NONE ) {
1.873 + CMP_imm8s_sh4r( 1, R_T );
1.874 + sh4_x86.tstate = TSTATE_E;
1.875 + }
1.876 + OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
1.877 sh4_x86_translate_instruction(pc+2);
1.878 exit_block( disp + pc + 4, pc+4 );
1.879 // not taken
1.880 @@ -1473,6 +1609,7 @@
1.881 sh4_x86.in_delay_slot = TRUE;
1.882 sh4_x86.priv_checked = FALSE;
1.883 sh4_x86.fpuen_checked = FALSE;
1.884 + sh4_x86.tstate = TSTATE_NONE;
1.885 sh4_x86_translate_instruction(pc+2);
1.886 exit_block_pcset(pc+2);
1.887 sh4_x86.branch_taken = TRUE;
1.888 @@ -1499,6 +1636,7 @@
1.889 PUSH_imm32( imm );
1.890 call_func0( sh4_raise_trap );
1.891 ADD_imm8s_r32( 4, R_ESP );
1.892 + sh4_x86.tstate = TSTATE_NONE;
1.893 exit_block_pcset(pc);
1.894 sh4_x86.branch_taken = TRUE;
1.895 return 2;
1.896 @@ -1518,22 +1656,27 @@
1.897 XOR_r32_r32(R_EAX, R_EAX);
1.898 store_spreg( R_EAX, R_MACL );
1.899 store_spreg( R_EAX, R_MACH );
1.900 + sh4_x86.tstate = TSTATE_NONE;
1.901 :}
1.902 CLRS {:
1.903 CLC();
1.904 SETC_sh4r(R_S);
1.905 + sh4_x86.tstate = TSTATE_C;
1.906 :}
1.907 CLRT {:
1.908 CLC();
1.909 SETC_t();
1.910 + sh4_x86.tstate = TSTATE_C;
1.911 :}
1.912 SETS {:
1.913 STC();
1.914 SETC_sh4r(R_S);
1.915 + sh4_x86.tstate = TSTATE_C;
1.916 :}
1.917 SETT {:
1.918 STC();
1.919 SETC_t();
1.920 + sh4_x86.tstate = TSTATE_C;
1.921 :}
1.922
1.923 /* Floating point moves */
1.924 @@ -1585,6 +1728,7 @@
1.925 JMP_TARGET(end);
1.926 }
1.927 }
1.928 + sh4_x86.tstate = TSTATE_NONE;
1.929 :}
1.930 FMOV FRm, @Rn {:
1.931 precheck();
1.932 @@ -1614,6 +1758,7 @@
1.933 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
1.934 JMP_TARGET(end);
1.935 }
1.936 + sh4_x86.tstate = TSTATE_NONE;
1.937 :}
1.938 FMOV @Rm, FRn {:
1.939 precheck();
1.940 @@ -1644,6 +1789,7 @@
1.941 store_fr( R_EDX, R_ECX, FRn|0x01 );
1.942 JMP_TARGET(end);
1.943 }
1.944 + sh4_x86.tstate = TSTATE_NONE;
1.945 :}
1.946 FMOV FRm, @-Rn {:
1.947 precheck();
1.948 @@ -1679,6 +1825,7 @@
1.949 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
1.950 JMP_TARGET(end);
1.951 }
1.952 + sh4_x86.tstate = TSTATE_NONE;
1.953 :}
1.954 FMOV @Rm+, FRn {:
1.955 precheck();
1.956 @@ -1715,6 +1862,7 @@
1.957 store_fr( R_EDX, R_ECX, FRn|0x01 );
1.958 JMP_TARGET(end);
1.959 }
1.960 + sh4_x86.tstate = TSTATE_NONE;
1.961 :}
1.962 FMOV FRm, @(R0, Rn) {:
1.963 precheck();
1.964 @@ -1745,6 +1893,7 @@
1.965 MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
1.966 JMP_TARGET(end);
1.967 }
1.968 + sh4_x86.tstate = TSTATE_NONE;
1.969 :}
1.970 FMOV @(R0, Rm), FRn {:
1.971 precheck();
1.972 @@ -1776,6 +1925,7 @@
1.973 store_fr( R_EDX, R_ECX, FRn|0x01 );
1.974 JMP_TARGET(end);
1.975 }
1.976 + sh4_x86.tstate = TSTATE_NONE;
1.977 :}
1.978 FLDI0 FRn {: /* IFF PR=0 */
1.979 check_fpuen();
1.980 @@ -1786,6 +1936,7 @@
1.981 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.982 store_fr( R_ECX, R_EAX, FRn );
1.983 JMP_TARGET(end);
1.984 + sh4_x86.tstate = TSTATE_NONE;
1.985 :}
1.986 FLDI1 FRn {: /* IFF PR=0 */
1.987 check_fpuen();
1.988 @@ -1796,6 +1947,7 @@
1.989 load_spreg( R_ECX, REG_OFFSET(fr_bank) );
1.990 store_fr( R_ECX, R_EAX, FRn );
1.991 JMP_TARGET(end);
1.992 + sh4_x86.tstate = TSTATE_NONE;
1.993 :}
1.994
1.995 FLOAT FPUL, FRn {:
1.996 @@ -1810,6 +1962,7 @@
1.997 JMP_TARGET(doubleprec);
1.998 pop_dr( R_EDX, FRn );
1.999 JMP_TARGET(end);
1.1000 + sh4_x86.tstate = TSTATE_NONE;
1.1001 :}
1.1002 FTRC FRm, FPUL {:
1.1003 check_fpuen();
1.1004 @@ -1844,18 +1997,21 @@
1.1005 store_spreg( R_ECX, R_FPUL );
1.1006 FPOP_st();
1.1007 JMP_TARGET(end);
1.1008 + sh4_x86.tstate = TSTATE_NONE;
1.1009 :}
1.1010 FLDS FRm, FPUL {:
1.1011 check_fpuen();
1.1012 load_fr_bank( R_ECX );
1.1013 load_fr( R_ECX, R_EAX, FRm );
1.1014 store_spreg( R_EAX, R_FPUL );
1.1015 + sh4_x86.tstate = TSTATE_NONE;
1.1016 :}
1.1017 FSTS FPUL, FRn {:
1.1018 check_fpuen();
1.1019 load_fr_bank( R_ECX );
1.1020 load_spreg( R_EAX, R_FPUL );
1.1021 store_fr( R_ECX, R_EAX, FRn );
1.1022 + sh4_x86.tstate = TSTATE_NONE;
1.1023 :}
1.1024 FCNVDS FRm, FPUL {:
1.1025 check_fpuen();
1.1026 @@ -1866,6 +2022,7 @@
1.1027 push_dr( R_ECX, FRm );
1.1028 pop_fpul();
1.1029 JMP_TARGET(end);
1.1030 + sh4_x86.tstate = TSTATE_NONE;
1.1031 :}
1.1032 FCNVSD FPUL, FRn {:
1.1033 check_fpuen();
1.1034 @@ -1876,6 +2033,7 @@
1.1035 push_fpul();
1.1036 pop_dr( R_ECX, FRn );
1.1037 JMP_TARGET(end);
1.1038 + sh4_x86.tstate = TSTATE_NONE;
1.1039 :}
1.1040
1.1041 /* Floating point instructions */
1.1042 @@ -1894,6 +2052,7 @@
1.1043 FABS_st0();
1.1044 pop_dr(R_EDX, FRn);
1.1045 JMP_TARGET(end);
1.1046 + sh4_x86.tstate = TSTATE_NONE;
1.1047 :}
1.1048 FADD FRm, FRn {:
1.1049 check_fpuen();
1.1050 @@ -1912,6 +2071,7 @@
1.1051 FADDP_st(1);
1.1052 pop_dr(R_EDX, FRn);
1.1053 JMP_TARGET(end);
1.1054 + sh4_x86.tstate = TSTATE_NONE;
1.1055 :}
1.1056 FDIV FRm, FRn {:
1.1057 check_fpuen();
1.1058 @@ -1930,6 +2090,7 @@
1.1059 FDIVP_st(1);
1.1060 pop_dr(R_EDX, FRn);
1.1061 JMP_TARGET(end);
1.1062 + sh4_x86.tstate = TSTATE_NONE;
1.1063 :}
1.1064 FMAC FR0, FRm, FRn {:
1.1065 check_fpuen();
1.1066 @@ -1952,6 +2113,7 @@
1.1067 FADDP_st(1);
1.1068 pop_dr( R_EDX, FRn );
1.1069 JMP_TARGET(end);
1.1070 + sh4_x86.tstate = TSTATE_NONE;
1.1071 :}
1.1072
1.1073 FMUL FRm, FRn {:
1.1074 @@ -1971,6 +2133,7 @@
1.1075 FMULP_st(1);
1.1076 pop_dr(R_EDX, FRn);
1.1077 JMP_TARGET(end);
1.1078 + sh4_x86.tstate = TSTATE_NONE;
1.1079 :}
1.1080 FNEG FRn {:
1.1081 check_fpuen();
1.1082 @@ -1987,6 +2150,7 @@
1.1083 FCHS_st0();
1.1084 pop_dr(R_EDX, FRn);
1.1085 JMP_TARGET(end);
1.1086 + sh4_x86.tstate = TSTATE_NONE;
1.1087 :}
1.1088 FSRRA FRn {:
1.1089 check_fpuen();
1.1090 @@ -2000,6 +2164,7 @@
1.1091 FDIVP_st(1);
1.1092 pop_fr(R_EDX, FRn);
1.1093 JMP_TARGET(end);
1.1094 + sh4_x86.tstate = TSTATE_NONE;
1.1095 :}
1.1096 FSQRT FRn {:
1.1097 check_fpuen();
1.1098 @@ -2016,6 +2181,7 @@
1.1099 FSQRT_st0();
1.1100 pop_dr(R_EDX, FRn);
1.1101 JMP_TARGET(end);
1.1102 + sh4_x86.tstate = TSTATE_NONE;
1.1103 :}
1.1104 FSUB FRm, FRn {:
1.1105 check_fpuen();
1.1106 @@ -2034,6 +2200,7 @@
1.1107 FSUBP_st(1);
1.1108 pop_dr(R_EDX, FRn);
1.1109 JMP_TARGET(end);
1.1110 + sh4_x86.tstate = TSTATE_NONE;
1.1111 :}
1.1112
1.1113 FCMP/EQ FRm, FRn {:
1.1114 @@ -2052,6 +2219,7 @@
1.1115 FCOMIP_st(1);
1.1116 SETE_t();
1.1117 FPOP_st();
1.1118 + sh4_x86.tstate = TSTATE_NONE;
1.1119 :}
1.1120 FCMP/GT FRm, FRn {:
1.1121 check_fpuen();
1.1122 @@ -2069,6 +2237,7 @@
1.1123 FCOMIP_st(1);
1.1124 SETA_t();
1.1125 FPOP_st();
1.1126 + sh4_x86.tstate = TSTATE_NONE;
1.1127 :}
1.1128
1.1129 FSCA FPUL, FRn {:
1.1130 @@ -2081,6 +2250,7 @@
1.1131 load_spreg( R_EDX, R_FPUL );
1.1132 call_func2( sh4_fsca, R_EDX, R_ECX );
1.1133 JMP_TARGET(doubleprec);
1.1134 + sh4_x86.tstate = TSTATE_NONE;
1.1135 :}
1.1136 FIPR FVm, FVn {:
1.1137 check_fpuen();
1.1138 @@ -2106,6 +2276,7 @@
1.1139 FADDP_st(1);
1.1140 pop_fr( R_ECX, (FVn<<2)+3);
1.1141 JMP_TARGET(doubleprec);
1.1142 + sh4_x86.tstate = TSTATE_NONE;
1.1143 :}
1.1144 FTRV XMTRX, FVn {:
1.1145 check_fpuen();
1.1146 @@ -2117,6 +2288,7 @@
1.1147 load_xf_bank( R_ECX ); // 12
1.1148 call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
1.1149 JMP_TARGET(doubleprec);
1.1150 + sh4_x86.tstate = TSTATE_NONE;
1.1151 :}
1.1152
1.1153 FRCHG {:
1.1154 @@ -2125,12 +2297,14 @@
1.1155 XOR_imm32_r32( FPSCR_FR, R_ECX );
1.1156 store_spreg( R_ECX, R_FPSCR );
1.1157 update_fr_bank( R_ECX );
1.1158 + sh4_x86.tstate = TSTATE_NONE;
1.1159 :}
1.1160 FSCHG {:
1.1161 check_fpuen();
1.1162 load_spreg( R_ECX, R_FPSCR );
1.1163 XOR_imm32_r32( FPSCR_SZ, R_ECX );
1.1164 store_spreg( R_ECX, R_FPSCR );
1.1165 + sh4_x86.tstate = TSTATE_NONE;
1.1166 :}
1.1167
1.1168 /* Processor control instructions */
1.1169 @@ -2143,6 +2317,7 @@
1.1170 call_func1( sh4_write_sr, R_EAX );
1.1171 sh4_x86.priv_checked = FALSE;
1.1172 sh4_x86.fpuen_checked = FALSE;
1.1173 + sh4_x86.tstate = TSTATE_NONE;
1.1174 }
1.1175 :}
1.1176 LDC Rm, GBR {:
1.1177 @@ -2153,31 +2328,37 @@
1.1178 check_priv();
1.1179 load_reg( R_EAX, Rm );
1.1180 store_spreg( R_EAX, R_VBR );
1.1181 + sh4_x86.tstate = TSTATE_NONE;
1.1182 :}
1.1183 LDC Rm, SSR {:
1.1184 check_priv();
1.1185 load_reg( R_EAX, Rm );
1.1186 store_spreg( R_EAX, R_SSR );
1.1187 + sh4_x86.tstate = TSTATE_NONE;
1.1188 :}
1.1189 LDC Rm, SGR {:
1.1190 check_priv();
1.1191 load_reg( R_EAX, Rm );
1.1192 store_spreg( R_EAX, R_SGR );
1.1193 + sh4_x86.tstate = TSTATE_NONE;
1.1194 :}
1.1195 LDC Rm, SPC {:
1.1196 check_priv();
1.1197 load_reg( R_EAX, Rm );
1.1198 store_spreg( R_EAX, R_SPC );
1.1199 + sh4_x86.tstate = TSTATE_NONE;
1.1200 :}
1.1201 LDC Rm, DBR {:
1.1202 check_priv();
1.1203 load_reg( R_EAX, Rm );
1.1204 store_spreg( R_EAX, R_DBR );
1.1205 + sh4_x86.tstate = TSTATE_NONE;
1.1206 :}
1.1207 LDC Rm, Rn_BANK {:
1.1208 check_priv();
1.1209 load_reg( R_EAX, Rm );
1.1210 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
1.1211 + sh4_x86.tstate = TSTATE_NONE;
1.1212 :}
1.1213 LDC.L @Rm+, GBR {:
1.1214 load_reg( R_EAX, Rm );
1.1215 @@ -2188,6 +2369,7 @@
1.1216 store_reg( R_EAX, Rm );
1.1217 MEM_READ_LONG( R_ECX, R_EAX );
1.1218 store_spreg( R_EAX, R_GBR );
1.1219 + sh4_x86.tstate = TSTATE_NONE;
1.1220 :}
1.1221 LDC.L @Rm+, SR {:
1.1222 if( sh4_x86.in_delay_slot ) {
1.1223 @@ -2204,6 +2386,7 @@
1.1224 call_func1( sh4_write_sr, R_EAX );
1.1225 sh4_x86.priv_checked = FALSE;
1.1226 sh4_x86.fpuen_checked = FALSE;
1.1227 + sh4_x86.tstate = TSTATE_NONE;
1.1228 }
1.1229 :}
1.1230 LDC.L @Rm+, VBR {:
1.1231 @@ -2216,6 +2399,7 @@
1.1232 store_reg( R_EAX, Rm );
1.1233 MEM_READ_LONG( R_ECX, R_EAX );
1.1234 store_spreg( R_EAX, R_VBR );
1.1235 + sh4_x86.tstate = TSTATE_NONE;
1.1236 :}
1.1237 LDC.L @Rm+, SSR {:
1.1238 precheck();
1.1239 @@ -2227,6 +2411,7 @@
1.1240 store_reg( R_EAX, Rm );
1.1241 MEM_READ_LONG( R_ECX, R_EAX );
1.1242 store_spreg( R_EAX, R_SSR );
1.1243 + sh4_x86.tstate = TSTATE_NONE;
1.1244 :}
1.1245 LDC.L @Rm+, SGR {:
1.1246 precheck();
1.1247 @@ -2238,6 +2423,7 @@
1.1248 store_reg( R_EAX, Rm );
1.1249 MEM_READ_LONG( R_ECX, R_EAX );
1.1250 store_spreg( R_EAX, R_SGR );
1.1251 + sh4_x86.tstate = TSTATE_NONE;
1.1252 :}
1.1253 LDC.L @Rm+, SPC {:
1.1254 precheck();
1.1255 @@ -2249,6 +2435,7 @@
1.1256 store_reg( R_EAX, Rm );
1.1257 MEM_READ_LONG( R_ECX, R_EAX );
1.1258 store_spreg( R_EAX, R_SPC );
1.1259 + sh4_x86.tstate = TSTATE_NONE;
1.1260 :}
1.1261 LDC.L @Rm+, DBR {:
1.1262 precheck();
1.1263 @@ -2260,6 +2447,7 @@
1.1264 store_reg( R_EAX, Rm );
1.1265 MEM_READ_LONG( R_ECX, R_EAX );
1.1266 store_spreg( R_EAX, R_DBR );
1.1267 + sh4_x86.tstate = TSTATE_NONE;
1.1268 :}
1.1269 LDC.L @Rm+, Rn_BANK {:
1.1270 precheck();
1.1271 @@ -2271,11 +2459,13 @@
1.1272 store_reg( R_EAX, Rm );
1.1273 MEM_READ_LONG( R_ECX, R_EAX );
1.1274 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
1.1275 + sh4_x86.tstate = TSTATE_NONE;
1.1276 :}
1.1277 LDS Rm, FPSCR {:
1.1278 load_reg( R_EAX, Rm );
1.1279 store_spreg( R_EAX, R_FPSCR );
1.1280 update_fr_bank( R_EAX );
1.1281 + sh4_x86.tstate = TSTATE_NONE;
1.1282 :}
1.1283 LDS.L @Rm+, FPSCR {:
1.1284 load_reg( R_EAX, Rm );
1.1285 @@ -2287,6 +2477,7 @@
1.1286 MEM_READ_LONG( R_ECX, R_EAX );
1.1287 store_spreg( R_EAX, R_FPSCR );
1.1288 update_fr_bank( R_EAX );
1.1289 + sh4_x86.tstate = TSTATE_NONE;
1.1290 :}
1.1291 LDS Rm, FPUL {:
1.1292 load_reg( R_EAX, Rm );
1.1293 @@ -2301,6 +2492,7 @@
1.1294 store_reg( R_EAX, Rm );
1.1295 MEM_READ_LONG( R_ECX, R_EAX );
1.1296 store_spreg( R_EAX, R_FPUL );
1.1297 + sh4_x86.tstate = TSTATE_NONE;
1.1298 :}
1.1299 LDS Rm, MACH {:
1.1300 load_reg( R_EAX, Rm );
1.1301 @@ -2315,6 +2507,7 @@
1.1302 store_reg( R_EAX, Rm );
1.1303 MEM_READ_LONG( R_ECX, R_EAX );
1.1304 store_spreg( R_EAX, R_MACH );
1.1305 + sh4_x86.tstate = TSTATE_NONE;
1.1306 :}
1.1307 LDS Rm, MACL {:
1.1308 load_reg( R_EAX, Rm );
1.1309 @@ -2329,6 +2522,7 @@
1.1310 store_reg( R_EAX, Rm );
1.1311 MEM_READ_LONG( R_ECX, R_EAX );
1.1312 store_spreg( R_EAX, R_MACL );
1.1313 + sh4_x86.tstate = TSTATE_NONE;
1.1314 :}
1.1315 LDS Rm, PR {:
1.1316 load_reg( R_EAX, Rm );
1.1317 @@ -2343,6 +2537,7 @@
1.1318 store_reg( R_EAX, Rm );
1.1319 MEM_READ_LONG( R_ECX, R_EAX );
1.1320 store_spreg( R_EAX, R_PR );
1.1321 + sh4_x86.tstate = TSTATE_NONE;
1.1322 :}
1.1323 LDTLB {: :}
1.1324 OCBI @Rn {: :}
1.1325 @@ -2357,10 +2552,12 @@
1.1326 call_func0( sh4_flush_store_queue );
1.1327 JMP_TARGET(end);
1.1328 ADD_imm8s_r32( 4, R_ESP );
1.1329 + sh4_x86.tstate = TSTATE_NONE;
1.1330 :}
1.1331 SLEEP {:
1.1332 check_priv();
1.1333 call_func0( sh4_sleep );
1.1334 + sh4_x86.tstate = TSTATE_NONE;
1.1335 sh4_x86.in_delay_slot = FALSE;
1.1336 return 2;
1.1337 :}
1.1338 @@ -2368,6 +2565,7 @@
1.1339 check_priv();
1.1340 call_func0(sh4_read_sr);
1.1341 store_reg( R_EAX, Rn );
1.1342 + sh4_x86.tstate = TSTATE_NONE;
1.1343 :}
1.1344 STC GBR, Rn {:
1.1345 load_spreg( R_EAX, R_GBR );
1.1346 @@ -2377,31 +2575,37 @@
1.1347 check_priv();
1.1348 load_spreg( R_EAX, R_VBR );
1.1349 store_reg( R_EAX, Rn );
1.1350 + sh4_x86.tstate = TSTATE_NONE;
1.1351 :}
1.1352 STC SSR, Rn {:
1.1353 check_priv();
1.1354 load_spreg( R_EAX, R_SSR );
1.1355 store_reg( R_EAX, Rn );
1.1356 + sh4_x86.tstate = TSTATE_NONE;
1.1357 :}
1.1358 STC SPC, Rn {:
1.1359 check_priv();
1.1360 load_spreg( R_EAX, R_SPC );
1.1361 store_reg( R_EAX, Rn );
1.1362 + sh4_x86.tstate = TSTATE_NONE;
1.1363 :}
1.1364 STC SGR, Rn {:
1.1365 check_priv();
1.1366 load_spreg( R_EAX, R_SGR );
1.1367 store_reg( R_EAX, Rn );
1.1368 + sh4_x86.tstate = TSTATE_NONE;
1.1369 :}
1.1370 STC DBR, Rn {:
1.1371 check_priv();
1.1372 load_spreg( R_EAX, R_DBR );
1.1373 store_reg( R_EAX, Rn );
1.1374 + sh4_x86.tstate = TSTATE_NONE;
1.1375 :}
1.1376 STC Rm_BANK, Rn {:
1.1377 check_priv();
1.1378 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
1.1379 store_reg( R_EAX, Rn );
1.1380 + sh4_x86.tstate = TSTATE_NONE;
1.1381 :}
1.1382 STC.L SR, @-Rn {:
1.1383 precheck();
1.1384 @@ -2412,6 +2616,7 @@
1.1385 ADD_imm8s_r32( -4, R_ECX );
1.1386 store_reg( R_ECX, Rn );
1.1387 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1388 + sh4_x86.tstate = TSTATE_NONE;
1.1389 :}
1.1390 STC.L VBR, @-Rn {:
1.1391 precheck();
1.1392 @@ -2422,6 +2627,7 @@
1.1393 store_reg( R_ECX, Rn );
1.1394 load_spreg( R_EAX, R_VBR );
1.1395 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1396 + sh4_x86.tstate = TSTATE_NONE;
1.1397 :}
1.1398 STC.L SSR, @-Rn {:
1.1399 precheck();
1.1400 @@ -2432,6 +2638,7 @@
1.1401 store_reg( R_ECX, Rn );
1.1402 load_spreg( R_EAX, R_SSR );
1.1403 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1404 + sh4_x86.tstate = TSTATE_NONE;
1.1405 :}
1.1406 STC.L SPC, @-Rn {:
1.1407 precheck();
1.1408 @@ -2442,6 +2649,7 @@
1.1409 store_reg( R_ECX, Rn );
1.1410 load_spreg( R_EAX, R_SPC );
1.1411 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1412 + sh4_x86.tstate = TSTATE_NONE;
1.1413 :}
1.1414 STC.L SGR, @-Rn {:
1.1415 precheck();
1.1416 @@ -2452,6 +2660,7 @@
1.1417 store_reg( R_ECX, Rn );
1.1418 load_spreg( R_EAX, R_SGR );
1.1419 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1420 + sh4_x86.tstate = TSTATE_NONE;
1.1421 :}
1.1422 STC.L DBR, @-Rn {:
1.1423 precheck();
1.1424 @@ -2462,6 +2671,7 @@
1.1425 store_reg( R_ECX, Rn );
1.1426 load_spreg( R_EAX, R_DBR );
1.1427 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1428 + sh4_x86.tstate = TSTATE_NONE;
1.1429 :}
1.1430 STC.L Rm_BANK, @-Rn {:
1.1431 precheck();
1.1432 @@ -2472,6 +2682,7 @@
1.1433 store_reg( R_ECX, Rn );
1.1434 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
1.1435 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1436 + sh4_x86.tstate = TSTATE_NONE;
1.1437 :}
1.1438 STC.L GBR, @-Rn {:
1.1439 load_reg( R_ECX, Rn );
1.1440 @@ -2481,6 +2692,7 @@
1.1441 store_reg( R_ECX, Rn );
1.1442 load_spreg( R_EAX, R_GBR );
1.1443 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1444 + sh4_x86.tstate = TSTATE_NONE;
1.1445 :}
1.1446 STS FPSCR, Rn {:
1.1447 load_spreg( R_EAX, R_FPSCR );
1.1448 @@ -2494,6 +2706,7 @@
1.1449 store_reg( R_ECX, Rn );
1.1450 load_spreg( R_EAX, R_FPSCR );
1.1451 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1452 + sh4_x86.tstate = TSTATE_NONE;
1.1453 :}
1.1454 STS FPUL, Rn {:
1.1455 load_spreg( R_EAX, R_FPUL );
1.1456 @@ -2507,6 +2720,7 @@
1.1457 store_reg( R_ECX, Rn );
1.1458 load_spreg( R_EAX, R_FPUL );
1.1459 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1460 + sh4_x86.tstate = TSTATE_NONE;
1.1461 :}
1.1462 STS MACH, Rn {:
1.1463 load_spreg( R_EAX, R_MACH );
1.1464 @@ -2520,6 +2734,7 @@
1.1465 store_reg( R_ECX, Rn );
1.1466 load_spreg( R_EAX, R_MACH );
1.1467 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1468 + sh4_x86.tstate = TSTATE_NONE;
1.1469 :}
1.1470 STS MACL, Rn {:
1.1471 load_spreg( R_EAX, R_MACL );
1.1472 @@ -2533,6 +2748,7 @@
1.1473 store_reg( R_ECX, Rn );
1.1474 load_spreg( R_EAX, R_MACL );
1.1475 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1476 + sh4_x86.tstate = TSTATE_NONE;
1.1477 :}
1.1478 STS PR, Rn {:
1.1479 load_spreg( R_EAX, R_PR );
1.1480 @@ -2546,6 +2762,7 @@
1.1481 store_reg( R_ECX, Rn );
1.1482 load_spreg( R_EAX, R_PR );
1.1483 MEM_WRITE_LONG( R_ECX, R_EAX );
1.1484 + sh4_x86.tstate = TSTATE_NONE;
1.1485 :}
1.1486
1.1487 NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
.