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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 395:c473acbde186
prev394:7eb172bfeefe
next397:640324505325
author nkeynes
date Wed Sep 19 10:04:16 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Add alignment checks to LDC.L/STC.L/LDS.L/STS.L
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Wed Sep 19 09:15:18 2007 +0000
1.2 +++ b/src/sh4/sh4x86.in Wed Sep 19 10:04:16 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4x86.in,v 1.12 2007-09-19 09:15:18 nkeynes Exp $
1.6 + * $Id: sh4x86.in,v 1.13 2007-09-19 10:04:16 nkeynes Exp $
1.7 *
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -2120,6 +2120,7 @@
1.11 :}
1.12 LDC.L @Rm+, GBR {:
1.13 load_reg( R_EAX, Rm );
1.14 + check_ralign32( R_EAX );
1.15 MOV_r32_r32( R_EAX, R_ECX );
1.16 ADD_imm8s_r32( 4, R_EAX );
1.17 store_reg( R_EAX, Rm );
1.18 @@ -2132,6 +2133,7 @@
1.19 } else {
1.20 check_priv();
1.21 load_reg( R_EAX, Rm );
1.22 + check_ralign32( R_EAX );
1.23 MOV_r32_r32( R_EAX, R_ECX );
1.24 ADD_imm8s_r32( 4, R_EAX );
1.25 store_reg( R_EAX, Rm );
1.26 @@ -2144,6 +2146,7 @@
1.27 LDC.L @Rm+, VBR {:
1.28 check_priv();
1.29 load_reg( R_EAX, Rm );
1.30 + check_ralign32( R_EAX );
1.31 MOV_r32_r32( R_EAX, R_ECX );
1.32 ADD_imm8s_r32( 4, R_EAX );
1.33 store_reg( R_EAX, Rm );
1.34 @@ -2162,6 +2165,7 @@
1.35 LDC.L @Rm+, SGR {:
1.36 check_priv();
1.37 load_reg( R_EAX, Rm );
1.38 + check_ralign32( R_EAX );
1.39 MOV_r32_r32( R_EAX, R_ECX );
1.40 ADD_imm8s_r32( 4, R_EAX );
1.41 store_reg( R_EAX, Rm );
1.42 @@ -2171,6 +2175,7 @@
1.43 LDC.L @Rm+, SPC {:
1.44 check_priv();
1.45 load_reg( R_EAX, Rm );
1.46 + check_ralign32( R_EAX );
1.47 MOV_r32_r32( R_EAX, R_ECX );
1.48 ADD_imm8s_r32( 4, R_EAX );
1.49 store_reg( R_EAX, Rm );
1.50 @@ -2180,6 +2185,7 @@
1.51 LDC.L @Rm+, DBR {:
1.52 check_priv();
1.53 load_reg( R_EAX, Rm );
1.54 + check_ralign32( R_EAX );
1.55 MOV_r32_r32( R_EAX, R_ECX );
1.56 ADD_imm8s_r32( 4, R_EAX );
1.57 store_reg( R_EAX, Rm );
1.58 @@ -2189,6 +2195,7 @@
1.59 LDC.L @Rm+, Rn_BANK {:
1.60 check_priv();
1.61 load_reg( R_EAX, Rm );
1.62 + check_ralign32( R_EAX );
1.63 MOV_r32_r32( R_EAX, R_ECX );
1.64 ADD_imm8s_r32( 4, R_EAX );
1.65 store_reg( R_EAX, Rm );
1.66 @@ -2202,6 +2209,7 @@
1.67 :}
1.68 LDS.L @Rm+, FPSCR {:
1.69 load_reg( R_EAX, Rm );
1.70 + check_ralign32( R_EAX );
1.71 MOV_r32_r32( R_EAX, R_ECX );
1.72 ADD_imm8s_r32( 4, R_EAX );
1.73 store_reg( R_EAX, Rm );
1.74 @@ -2215,6 +2223,7 @@
1.75 :}
1.76 LDS.L @Rm+, FPUL {:
1.77 load_reg( R_EAX, Rm );
1.78 + check_ralign32( R_EAX );
1.79 MOV_r32_r32( R_EAX, R_ECX );
1.80 ADD_imm8s_r32( 4, R_EAX );
1.81 store_reg( R_EAX, Rm );
1.82 @@ -2227,6 +2236,7 @@
1.83 :}
1.84 LDS.L @Rm+, MACH {:
1.85 load_reg( R_EAX, Rm );
1.86 + check_ralign32( R_EAX );
1.87 MOV_r32_r32( R_EAX, R_ECX );
1.88 ADD_imm8s_r32( 4, R_EAX );
1.89 store_reg( R_EAX, Rm );
1.90 @@ -2239,6 +2249,7 @@
1.91 :}
1.92 LDS.L @Rm+, MACL {:
1.93 load_reg( R_EAX, Rm );
1.94 + check_ralign32( R_EAX );
1.95 MOV_r32_r32( R_EAX, R_ECX );
1.96 ADD_imm8s_r32( 4, R_EAX );
1.97 store_reg( R_EAX, Rm );
1.98 @@ -2251,6 +2262,7 @@
1.99 :}
1.100 LDS.L @Rm+, PR {:
1.101 load_reg( R_EAX, Rm );
1.102 + check_ralign32( R_EAX );
1.103 MOV_r32_r32( R_EAX, R_ECX );
1.104 ADD_imm8s_r32( 4, R_EAX );
1.105 store_reg( R_EAX, Rm );
1.106 @@ -2320,15 +2332,17 @@
1.107 :}
1.108 STC.L SR, @-Rn {:
1.109 check_priv();
1.110 + call_func0( sh4_read_sr );
1.111 load_reg( R_ECX, Rn );
1.112 + check_walign32( R_ECX );
1.113 ADD_imm8s_r32( -4, R_ECX );
1.114 store_reg( R_ECX, Rn );
1.115 - call_func0( sh4_read_sr );
1.116 MEM_WRITE_LONG( R_ECX, R_EAX );
1.117 :}
1.118 STC.L VBR, @-Rn {:
1.119 check_priv();
1.120 load_reg( R_ECX, Rn );
1.121 + check_walign32( R_ECX );
1.122 ADD_imm8s_r32( -4, R_ECX );
1.123 store_reg( R_ECX, Rn );
1.124 load_spreg( R_EAX, R_VBR );
1.125 @@ -2337,6 +2351,7 @@
1.126 STC.L SSR, @-Rn {:
1.127 check_priv();
1.128 load_reg( R_ECX, Rn );
1.129 + check_walign32( R_ECX );
1.130 ADD_imm8s_r32( -4, R_ECX );
1.131 store_reg( R_ECX, Rn );
1.132 load_spreg( R_EAX, R_SSR );
1.133 @@ -2345,6 +2360,7 @@
1.134 STC.L SPC, @-Rn {:
1.135 check_priv();
1.136 load_reg( R_ECX, Rn );
1.137 + check_walign32( R_ECX );
1.138 ADD_imm8s_r32( -4, R_ECX );
1.139 store_reg( R_ECX, Rn );
1.140 load_spreg( R_EAX, R_SPC );
1.141 @@ -2353,6 +2369,7 @@
1.142 STC.L SGR, @-Rn {:
1.143 check_priv();
1.144 load_reg( R_ECX, Rn );
1.145 + check_walign32( R_ECX );
1.146 ADD_imm8s_r32( -4, R_ECX );
1.147 store_reg( R_ECX, Rn );
1.148 load_spreg( R_EAX, R_SGR );
1.149 @@ -2361,6 +2378,7 @@
1.150 STC.L DBR, @-Rn {:
1.151 check_priv();
1.152 load_reg( R_ECX, Rn );
1.153 + check_walign32( R_ECX );
1.154 ADD_imm8s_r32( -4, R_ECX );
1.155 store_reg( R_ECX, Rn );
1.156 load_spreg( R_EAX, R_DBR );
1.157 @@ -2369,6 +2387,7 @@
1.158 STC.L Rm_BANK, @-Rn {:
1.159 check_priv();
1.160 load_reg( R_ECX, Rn );
1.161 + check_walign32( R_ECX );
1.162 ADD_imm8s_r32( -4, R_ECX );
1.163 store_reg( R_ECX, Rn );
1.164 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
1.165 @@ -2376,6 +2395,7 @@
1.166 :}
1.167 STC.L GBR, @-Rn {:
1.168 load_reg( R_ECX, Rn );
1.169 + check_walign32( R_ECX );
1.170 ADD_imm8s_r32( -4, R_ECX );
1.171 store_reg( R_ECX, Rn );
1.172 load_spreg( R_EAX, R_GBR );
1.173 @@ -2387,6 +2407,7 @@
1.174 :}
1.175 STS.L FPSCR, @-Rn {:
1.176 load_reg( R_ECX, Rn );
1.177 + check_walign32( R_ECX );
1.178 ADD_imm8s_r32( -4, R_ECX );
1.179 store_reg( R_ECX, Rn );
1.180 load_spreg( R_EAX, R_FPSCR );
1.181 @@ -2398,6 +2419,7 @@
1.182 :}
1.183 STS.L FPUL, @-Rn {:
1.184 load_reg( R_ECX, Rn );
1.185 + check_walign32( R_ECX );
1.186 ADD_imm8s_r32( -4, R_ECX );
1.187 store_reg( R_ECX, Rn );
1.188 load_spreg( R_EAX, R_FPUL );
1.189 @@ -2409,6 +2431,7 @@
1.190 :}
1.191 STS.L MACH, @-Rn {:
1.192 load_reg( R_ECX, Rn );
1.193 + check_walign32( R_ECX );
1.194 ADD_imm8s_r32( -4, R_ECX );
1.195 store_reg( R_ECX, Rn );
1.196 load_spreg( R_EAX, R_MACH );
1.197 @@ -2420,6 +2443,7 @@
1.198 :}
1.199 STS.L MACL, @-Rn {:
1.200 load_reg( R_ECX, Rn );
1.201 + check_walign32( R_ECX );
1.202 ADD_imm8s_r32( -4, R_ECX );
1.203 store_reg( R_ECX, Rn );
1.204 load_spreg( R_EAX, R_MACL );
1.205 @@ -2431,6 +2455,7 @@
1.206 :}
1.207 STS.L PR, @-Rn {:
1.208 load_reg( R_ECX, Rn );
1.209 + check_walign32( R_ECX );
1.210 ADD_imm8s_r32( -4, R_ECX );
1.211 store_reg( R_ECX, Rn );
1.212 load_spreg( R_EAX, R_PR );
.