1.1 --- a/src/sh4/mmu.c Wed Oct 29 23:51:58 2008 +0000
1.2 +++ b/src/sh4/mmu.c Fri Oct 31 03:24:49 2008 +0000
1.3 @@ -920,48 +920,54 @@
1.7 -gboolean FASTCALL sh4_flush_store_queue( sh4addr_t addr )
1.8 +void FASTCALL sh4_flush_store_queue( sh4addr_t addr )
1.10 + int queue = (addr&0x20)>>2;
1.11 + uint32_t hi = MMIO_READ( MMU, QACR0 + (queue>>1)) << 24;
1.12 + sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
1.13 + sh4addr_t target = (addr&0x03FFFFE0) | hi;
1.14 + mem_copy_to_sh4( target, src, 32 );
1.17 +gboolean FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr )
1.19 uint32_t mmucr = MMIO_READ(MMU,MMUCR);
1.20 int queue = (addr&0x20)>>2;
1.21 sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
1.23 /* Store queue operation */
1.24 - if( mmucr & MMUCR_AT ) {
1.26 - if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
1.27 - entryNo = mmu_utlb_lookup_vpn_asid( addr );
1.29 - entryNo = mmu_utlb_lookup_vpn( addr );
1.33 - MMU_TLB_WRITE_MISS_ERROR(addr);
1.36 - MMU_TLB_MULTI_HIT_ERROR(addr);
1.39 - if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
1.40 - : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
1.41 - /* protection violation */
1.42 - MMU_TLB_WRITE_PROT_ERROR(addr);
1.46 - if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
1.47 - MMU_TLB_INITIAL_WRITE_ERROR(addr);
1.51 + if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
1.52 + entryNo = mmu_utlb_lookup_vpn_asid( addr );
1.54 + entryNo = mmu_utlb_lookup_vpn( addr );
1.58 + MMU_TLB_WRITE_MISS_ERROR(addr);
1.61 + MMU_TLB_MULTI_HIT_ERROR(addr);
1.64 + if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
1.65 + : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
1.66 + /* protection violation */
1.67 + MMU_TLB_WRITE_PROT_ERROR(addr);
1.71 - /* finally generate the target address */
1.72 - target = ((mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) |
1.73 - (addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;
1.76 - uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
1.77 - target = (addr&0x03FFFFE0) | hi;
1.78 + if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
1.79 + MMU_TLB_INITIAL_WRITE_ERROR(addr);
1.83 + /* finally generate the target address */
1.84 + target = ((mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) |
1.85 + (addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;
1.88 mem_copy_to_sh4( target, src, 32 );