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lxdream.org :: lxdream/src/sh4/sh4.def :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.def
changeset 359:c588dce7ebde
author nkeynes
date Thu Aug 23 12:33:27 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Commit decoder generator
Translator work in progress
Fix mac.l, mac.w in emu core
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/sh4/sh4.def Thu Aug 23 12:33:27 2007 +0000
1.3 @@ -0,0 +1,236 @@
1.4 +##
1.5 +## Instruction file for the SH4 - from the SH4 manual.
1.6 +## line ::= bitpattern WHITESPACE result NEWLINE
1.7 +## bitpattern ::= { '0' | '1' | '(' operand ')' }
1.8 +## operand ::= IDENTIFIER ':' NUMBER signspec
1.9 +## signspec ::= 'u' | 's' |
1.10 +## result ::= { IDENTIFIER | NON-IDENT-CHAR }
1.11 +
1.12 +registers {
1.13 + uint32 Rm, Rn = r0..r15
1.14 + uint32 Rm_BANK, Rn_BANK = r8_bank..r15_bank
1.15 + float Frm, Frn = fr0..fr15
1.16 + float XFm, XFn = xf0..xf15
1.17 + double Drm, Drn = dr0..dr8 overlaps fr0..fr15 swapped
1.18 + double XDm, XDn = xd0..xd8 overlaps xf0..xf15 swapped
1.19 + float[4] FVm, FVn = fv0..fv3 overlaps fr0..fr15
1.20 + float[16] XMTRX = xmtrx overlaps xf0..xf15
1.21 +
1.22 +## Special registers
1.23 + uint32 GBR, SR, VBR, SSR, SGR SPC, DBR
1.24 + uint32 FPSCR, FPUL, MACH, MACL, PR, PC
1.25 +
1.26 +}
1.27 +
1.28 +0011(Rn:4)(Rm:4)1100 ADD Rm, Rn
1.29 +0111(Rn:4)(imm:8s) ADD #imm, Rn
1.30 +0011(Rn:4)(Rm:4)1110 ADDC Rm, Rn
1.31 +0011(Rn:4)(Rm:4)1111 ADDV Rm, Rn
1.32 +0010(Rn:4)(Rm:4)1001 AND Rm, Rn
1.33 +11001001(imm:8u) AND #imm, R0
1.34 +11001101(imm:8u) AND.B #imm, @(R0, GBR)
1.35 +10001011(disp:8s<<1) BF disp
1.36 +10001111(disp:8s<<1) BF/S disp
1.37 +1010(disp:12s<<1) BRA disp
1.38 +0000(Rn:4)00100011 BRAF Rn
1.39 +1011(disp:12s<<1) BSR disp
1.40 +0000(Rn:4)00000011 BSRF Rn
1.41 +10001001(disp:8s<<1) BT disp
1.42 +10001101(disp:8s<<1) BT/S disp
1.43 +0000000000101000 CLRMAC
1.44 +0000000001001000 CLRS
1.45 +0000000000001000 CLRT
1.46 +0011(Rn:4)(Rm:4)0000 CMP/EQ Rm, Rn
1.47 +10001000(imm:8s) CMP/EQ #imm, R0
1.48 +0011(Rn:4)(Rm:4)0011 CMP/GE Rm, Rn
1.49 +0011(Rn:4)(Rm:4)0111 CMP/GT Rm, Rn
1.50 +0011(Rn:4)(Rm:4)0110 CMP/HI Rm, Rn
1.51 +0011(Rn:4)(Rm:4)0010 CMP/HS Rm, Rn
1.52 +0100(Rn:4)00010101 CMP/PL Rn
1.53 +0100(Rn:4)00010001 CMP/PZ Rn
1.54 +0010(Rn:4)(Rm:4)1100 CMP/STR Rm, Rn
1.55 +0010(Rn:4)(Rm:4)0111 DIV0S Rm, Rn
1.56 +0000000000011001 DIV0U
1.57 +0011(Rn:4)(Rm:4)0100 DIV1 Rm, Rn
1.58 +0011(Rn:4)(Rm:4)1101 DMULS.L Rm, Rn
1.59 +0011(Rn:4)(Rm:4)0101 DMULU.L Rm, Rn
1.60 +0100(Rn:4)00010000 DT Rn
1.61 +0110(Rn:4)(Rm:4)1110 EXTS.B Rm, Rn
1.62 +0110(Rn:4)(Rm:4)1111 EXTS.W Rm, Rn
1.63 +0110(Rn:4)(Rm:4)1100 EXTU.B Rm, Rn
1.64 +0110(Rn:4)(Rm:4)1101 EXTU.W Rm, Rn
1.65 +1111(FRn:4)01011101 FABS FRn
1.66 +1111(FRn:4)(FRm:4)0000 FADD FRm, FRn
1.67 +1111(FRn:4)(FRm:4)0100 FCMP/EQ FRm, FRn
1.68 +1111(FRn:4)(FRm:4)0101 FCMP/GT FRm, FRn
1.69 +1111(FRm:4)10111101 FCNVDS FRm, FPUL
1.70 +1111(FRn:4)10101101 FCNVSD FPUL, FRn
1.71 +1111(FRn:4)(FRm:4)0011 FDIV FRm, FRn
1.72 +1111(FVn:2)(FVm:2)11101101 FIPR FVm, FVn
1.73 +1111(FRm:4)00011101 FLDS FRm, FPUL
1.74 +1111(FRn:4)10001101 FLDI0 FRn
1.75 +1111(FRn:4)10011101 FLDI1 FRn
1.76 +1111(FRn:4)00101101 FLOAT FPUL, FRn
1.77 +1111(FRn:4)(FRm:4)1110 FMAC FR0, FRm, FRn
1.78 +1111(FRn:4)(FRm:4)1100 FMOV FRm, FRn
1.79 +1111(Rn:4)(FRm:4)1010 FMOV FRm, @Rn
1.80 +1111(Rn:4)(FRm:4)1011 FMOV FRm, @-Rn
1.81 +1111(Rn:4)(FRm:4)0111 FMOV FRm, @(R0, Rn)
1.82 +1111(FRn:4)(Rm:4)1000 FMOV @Rm, FRn
1.83 +1111(FRn:4)(Rm:4)1001 FMOV @Rm+, FRn
1.84 +1111(FRn:4)(Rm:4)0110 FMOV @(R0, Rm), FRn
1.85 +1111(FRn:4)(FRm:4)0010 FMUL FRm, FRn
1.86 +1111(FRn:4)01001101 FNEG FRn
1.87 +1111101111111101 FRCHG
1.88 +1111(FRn:3<<1)011111101 FSCA FPUL, FRn
1.89 +1111001111111101 FSCHG
1.90 +1111(FRn:4)01101101 FSQRT FRn
1.91 +1111(FRn:4)01111101 FSRRA FRn
1.92 +1111(FRn:4)00001101 FSTS FPUL, FRn
1.93 +1111(FRn:4)(FRm:4)0001 FSUB FRm, FRn
1.94 +1111(FRm:4)00111101 FTRC FRm, FPUL
1.95 +1111(FVn:2)0111111101 FTRV XMTRX, FVn
1.96 +0100(Rn:4)00101011 JMP @Rn
1.97 +0100(Rn:4)00001011 JSR @Rn
1.98 +0100(Rm:4)00011110 LDC Rm, GBR
1.99 +0100(Rm:4)00001110 LDC Rm, SR
1.100 +0100(Rm:4)00101110 LDC Rm, VBR
1.101 +0100(Rm:4)00111110 LDC Rm, SSR
1.102 +0100(Rm:4)00111010 LDC Rm, SGR
1.103 +0100(Rm:4)01001110 LDC Rm, SPC
1.104 +0100(Rm:4)11111010 LDC Rm, DBR
1.105 +0100(Rm:4)1(Rn_BANK:3)1110 LDC Rm, Rn_BANK
1.106 +0100(Rm:4)00010111 LDC.L @Rm+, GBR
1.107 +0100(Rm:4)00000111 LDC.L @Rm+, SR
1.108 +0100(Rm:4)00100111 LDC.L @Rm+, VBR
1.109 +0100(Rm:4)00110111 LDC.L @Rm+, SSR
1.110 +0100(Rm:4)00110110 LDC.L @Rm+, SGR
1.111 +0100(Rm:4)01000111 LDC.L @Rm+, SPC
1.112 +0100(Rm:4)11110110 LDC.L @Rm+, DBR
1.113 +0100(Rm:4)1(Rn_BANK:3)0111 LDC.L @Rm+, Rn_BANK
1.114 +0100(Rm:4)01101010 LDS Rm, FPSCR
1.115 +0100(Rm:4)01100110 LDS.L @Rm+, FPSCR
1.116 +0100(Rm:4)01011010 LDS Rm, FPUL
1.117 +0100(Rm:4)01010110 LDS.L @Rm+, FPUL
1.118 +0100(Rm:4)00001010 LDS Rm, MACH
1.119 +0100(Rm:4)00000110 LDS.L @Rm+, MACH
1.120 +0100(Rm:4)00011010 LDS Rm, MACL
1.121 +0100(Rm:4)00010110 LDS.L @Rm+, MACL
1.122 +0100(Rm:4)00101010 LDS Rm, PR
1.123 +0100(Rm:4)00100110 LDS.L @Rm+, PR
1.124 +0000000000111000 LDTLB
1.125 +0000(Rn:4)(Rm:4)1111 MAC.L @Rm+, @Rn+
1.126 +0100(Rn:4)(Rm:4)1111 MAC.W @Rm+, @Rn+
1.127 +0110(Rn:4)(Rm:4)0011 MOV Rm, Rn
1.128 +1110(Rn:4)(imm:8s) MOV #imm, Rn
1.129 +0010(Rn:4)(Rm:4)0000 MOV.B Rm, @Rn
1.130 +0010(Rn:4)(Rm:4)0100 MOV.B Rm, @-Rn
1.131 +0000(Rn:4)(Rm:4)0100 MOV.B Rm, @(R0, Rn)
1.132 +11000000(disp:8) MOV.B R0, @(disp, GBR)
1.133 +10000000(Rn:4)(disp:4) MOV.B R0, @(disp, Rn)
1.134 +0110(Rn:4)(Rm:4)0000 MOV.B @Rm, Rn
1.135 +0110(Rn:4)(Rm:4)0100 MOV.B @Rm+, Rn
1.136 +0000(Rn:4)(Rm:4)1100 MOV.B @(R0, Rm), Rn
1.137 +11000100(disp:8) MOV.B @(disp, GBR), R0
1.138 +10000100(Rm:4)(disp:4) MOV.B @(disp, Rm), R0
1.139 +0010(Rn:4)(Rm:4)0010 MOV.L Rm, @Rn
1.140 +0010(Rn:4)(Rm:4)0110 MOV.L Rm, @-Rn
1.141 +0000(Rn:4)(Rm:4)0110 MOV.L Rm, @(R0, Rn)
1.142 +11000010(disp:8<<2) MOV.L R0, @(disp, GBR)
1.143 +0001(Rn:4)(Rm:4)(disp:4<<2) MOV.L Rm, @(disp, Rn)
1.144 +0110(Rn:4)(Rm:4)0010 MOV.L @Rm, Rn
1.145 +0110(Rn:4)(Rm:4)0110 MOV.L @Rm+, Rn
1.146 +0000(Rn:4)(Rm:4)1110 MOV.L @(R0, Rm), Rn
1.147 +11000110(disp:8<<2) MOV.L @(disp, GBR), R0
1.148 +1101(Rn:4)(disp:8<<2) MOV.L @(disp, PC), Rn
1.149 +0101(Rn:4)(Rm:4)(disp:4<<2) MOV.L @(disp, Rm), Rn
1.150 +0010(Rn:4)(Rm:4)0001 MOV.W Rm, @Rn
1.151 +0010(Rn:4)(Rm:4)0101 MOV.W Rm, @-Rn
1.152 +0000(Rn:4)(Rm:4)0101 MOV.W Rm, @(R0, Rn)
1.153 +11000001(disp:8<<1) MOV.W R0, @(disp, GBR)
1.154 +10000001(Rn:4)(disp:4<<1) MOV.W R0, @(disp, Rn)
1.155 +0110(Rn:4)(Rm:4)0001 MOV.W @Rm, Rn
1.156 +0110(Rn:4)(Rm:4)0101 MOV.W @Rm+, Rn
1.157 +0000(Rn:4)(Rm:4)1101 MOV.W @(R0, Rm), Rn
1.158 +11000101(disp:8<<1) MOV.W @(disp, GBR), R0
1.159 +1001(Rn:4)(disp:8<<1) MOV.W @(disp, PC), Rn
1.160 +10000101(Rm:4)(disp:4<<1) MOV.W @(disp, Rm), R0
1.161 +11000111(disp:8<<2) MOVA @(disp, PC), R0
1.162 +0000(Rn:4)11000011 MOVCA.L R0, @Rn
1.163 +0000(Rn:4)00101001 MOVT Rn
1.164 +0000(Rn:4)(Rm:4)0111 MUL.L Rm, Rn
1.165 +0010(Rn:4)(Rm:4)1111 MULS.W Rm, Rn
1.166 +0010(Rn:4)(Rm:4)1110 MULU.W Rm, Rn
1.167 +0110(Rn:4)(Rm:4)1011 NEG Rm, Rn
1.168 +0110(Rn:4)(Rm:4)1010 NEGC Rm, Rn
1.169 +0000000000001001 NOP
1.170 +0110(Rn:4)(Rm:4)0111 NOT Rm, Rn
1.171 +0000(Rn:4)10010011 OCBI @Rn
1.172 +0000(Rn:4)10100011 OCBP @Rn
1.173 +0000(Rn:4)10110011 OCBWB @Rn
1.174 +0010(Rn:4)(Rm:4)1011 OR Rm, Rn
1.175 +11001011(imm:8) OR #imm, R0
1.176 +11001111(imm:8) OR.B #imm, @(R0, GBR)
1.177 +0000(Rn:4)10000011 PREF @Rn
1.178 +0100(Rn:4)00100100 ROTCL Rn
1.179 +0100(Rn:4)00100101 ROTCR Rn
1.180 +0100(Rn:4)00000100 ROTL Rn
1.181 +0100(Rn:4)00000101 ROTR Rn
1.182 +0000000000101011 RTE
1.183 +0000000000001011 RTS
1.184 +0000000001011000 SETS
1.185 +0000000000011000 SETT
1.186 +0100(Rn:4)(Rm:4)1100 SHAD Rm, Rn
1.187 +0100(Rn:4)00100000 SHAL Rn
1.188 +0100(Rn:4)00100001 SHAR Rn
1.189 +0100(Rn:4)(Rm:4)1101 SHLD Rm, Rn
1.190 +0100(Rn:4)00000000 SHLL Rn
1.191 +0100(Rn:4)00001000 SHLL2 Rn
1.192 +0100(Rn:4)00011000 SHLL8 Rn
1.193 +0100(Rn:4)00101000 SHLL16 Rn
1.194 +0100(Rn:4)00000001 SHLR Rn
1.195 +0100(Rn:4)00001001 SHLR2 Rn
1.196 +0100(Rn:4)00011001 SHLR8 Rn
1.197 +0100(Rn:4)00101001 SHLR16 Rn
1.198 +0000000000011011 SLEEP
1.199 +0000(Rn:4)00000010 STC SR, Rn
1.200 +0000(Rn:4)00010010 STC GBR, Rn
1.201 +0000(Rn:4)00100010 STC VBR, Rn
1.202 +0000(Rn:4)00110010 STC SSR, Rn
1.203 +0000(Rn:4)01000010 STC SPC, Rn
1.204 +0000(Rn:4)00111010 STC SGR, Rn
1.205 +0000(Rn:4)11111010 STC DBR, Rn
1.206 +0000(Rn:4)1(Rm_BANK:3)0010 STC Rm_BANK, Rn
1.207 +0100(Rn:4)00000011 STC.L SR, @-Rn
1.208 +0100(Rn:4)00100011 STC.L VBR, @-Rn
1.209 +0100(Rn:4)00110011 STC.L SSR, @-Rn
1.210 +0100(Rn:4)01000011 STC.L SPC, @-Rn
1.211 +0100(Rn:4)00110010 STC.L SGR, @-Rn
1.212 +0100(Rn:4)11110010 STC.L DBR, @-Rn
1.213 +0100(Rn:4)1(Rm_BANK:3)0011 STC.L Rm_BANK, @-Rn
1.214 +0100(Rn:4)00010011 STC.L GBR, @-Rn
1.215 +0000(Rn:4)01101010 STS FPSCR, Rn
1.216 +0100(Rn:4)01100010 STS.L FPSCR, @-Rn
1.217 +0000(Rn:4)01011010 STS FPUL, Rn
1.218 +0100(Rn:4)01010010 STS.L FPUL, @-Rn
1.219 +0000(Rn:4)00001010 STS MACH, Rn
1.220 +0100(Rn:4)00000010 STS.L MACH, @-Rn
1.221 +0000(Rn:4)00011010 STS MACL, Rn
1.222 +0100(Rn:4)00010010 STS.L MACL, @-Rn
1.223 +0000(Rn:4)00101010 STS PR, Rn
1.224 +0100(Rn:4)00100010 STS.L PR, @-Rn
1.225 +0011(Rn:4)(Rm:4)1000 SUB Rm, Rn
1.226 +0011(Rn:4)(Rm:4)1010 SUBC Rm, Rn
1.227 +0011(Rn:4)(Rm:4)1011 SUBV Rm, Rn
1.228 +0110(Rn:4)(Rm:4)1000 SWAP.B Rm, Rn
1.229 +0110(Rn:4)(Rm:4)1001 SWAP.W Rm, Rn
1.230 +0100(Rn:4)00011011 TAS.B @Rn
1.231 +11000011(imm:8) TRAPA #imm
1.232 +0010(Rn:4)(Rm:4)1000 TST Rm, Rn
1.233 +11001000(imm:8) TST #imm, R0
1.234 +11001100(imm:8) TST.B #imm, @(R0, GBR)
1.235 +0010(Rn:4)(Rm:4)1010 XOR Rm, Rn
1.236 +11001010(imm:8) XOR #imm, R0
1.237 +11001110(imm:8) XOR.B #imm, @(R0, GBR)
1.238 +0010(Rn:4)(Rm:4)1101 XTRCT Rm, Rn
1.239 +1111111111111101 UNDEF
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