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lxdream.org :: lxdream/src/sh4/sh4x86.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 359:c588dce7ebde
next361:be3de4ecd954
author nkeynes
date Thu Aug 23 12:33:27 2007 +0000 (14 years ago)
permissions -rw-r--r--
last change Commit decoder generator
Translator work in progress
Fix mac.l, mac.w in emu core
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/sh4/sh4x86.c Thu Aug 23 12:33:27 2007 +0000
1.3 @@ -0,0 +1,1779 @@
1.4 +/**
1.5 + * $Id: sh4x86.c,v 1.1 2007-08-23 12:33:27 nkeynes Exp $
1.6 + *
1.7 + * SH4 => x86 translation. This version does no real optimization, it just
1.8 + * outputs straight-line x86 code - it mainly exists to provide a baseline
1.9 + * to test the optimizing versions against.
1.10 + *
1.11 + * Copyright (c) 2007 Nathan Keynes.
1.12 + *
1.13 + * This program is free software; you can redistribute it and/or modify
1.14 + * it under the terms of the GNU General Public License as published by
1.15 + * the Free Software Foundation; either version 2 of the License, or
1.16 + * (at your option) any later version.
1.17 + *
1.18 + * This program is distributed in the hope that it will be useful,
1.19 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.20 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.21 + * GNU General Public License for more details.
1.22 + */
1.23 +
1.24 +#include "sh4core.h"
1.25 +#include "sh4trans.h"
1.26 +#include "x86op.h"
1.27 +
1.28 +/**
1.29 + * Emit an instruction to load an SH4 reg into a real register
1.30 + */
1.31 +static inline void load_reg( int x86reg, int sh4reg )
1.32 +{
1.33 + /* mov [bp+n], reg */
1.34 + OP(0x89);
1.35 + OP(0x45 + x86reg<<3);
1.36 + OP(REG_OFFSET(r[sh4reg]));
1.37 +}
1.38 +
1.39 +static inline void load_spreg( int x86reg, int regoffset )
1.40 +{
1.41 + /* mov [bp+n], reg */
1.42 + OP(0x89);
1.43 + OP(0x45 + x86reg<<3);
1.44 + OP(regoffset);
1.45 +}
1.46 +
1.47 +#define UNDEF()
1.48 +#define MEM_READ_BYTE( addr_reg, value_reg )
1.49 +#define MEM_READ_WORD( addr_reg, value_reg )
1.50 +#define MEM_READ_LONG( addr_reg, value_reg )
1.51 +#define MEM_WRITE_BYTE( addr_reg, value_reg )
1.52 +#define MEM_WRITE_WORD( addr_reg, value_reg )
1.53 +#define MEM_WRITE_LONG( addr_reg, value_reg )
1.54 +
1.55 +/**
1.56 + * Emit an instruction to load an immediate value into a register
1.57 + */
1.58 +static inline void load_imm32( int x86reg, uint32_t value ) {
1.59 + /* mov #value, reg */
1.60 + OP(0xB8 + x86reg);
1.61 + OP32(value);
1.62 +}
1.63 +
1.64 +/**
1.65 + * Emit an instruction to store an SH4 reg (RN)
1.66 + */
1.67 +void static inline store_reg( int x86reg, int sh4reg ) {
1.68 + /* mov reg, [bp+n] */
1.69 + OP(0x8B);
1.70 + OP(0x45 + x86reg<<3);
1.71 + OP(REG_OFFSET(r[sh4reg]));
1.72 +}
1.73 +void static inline store_spreg( int x86reg, int regoffset ) {
1.74 + /* mov reg, [bp+n] */
1.75 + OP(0x8B);
1.76 + OP(0x45 + x86reg<<3);
1.77 + OP(regoffset);
1.78 +}
1.79 +
1.80 +
1.81 +/**
1.82 + * Emit the 'start of block' assembly. Sets up the stack frame and save
1.83 + * SI/DI as required
1.84 + */
1.85 +void sh4_translate_begin_block() {
1.86 + /* push ebp */
1.87 + *xlat_output++ = 0x50 + R_EBP;
1.88 +
1.89 + /* mov &sh4r, ebp */
1.90 + load_imm32( R_EBP, (uint32_t)&sh4r );
1.91 +
1.92 + /* load carry from SR */
1.93 +}
1.94 +
1.95 +/**
1.96 + * Flush any open regs back to memory, restore SI/DI/, update PC, etc
1.97 + */
1.98 +void sh4_translate_end_block( sh4addr_t pc ) {
1.99 + /* pop ebp */
1.100 + *xlat_output++ = 0x58 + R_EBP;
1.101 +
1.102 + /* ret */
1.103 + *xlat_output++ = 0xC3;
1.104 +}
1.105 +
1.106 +/**
1.107 + * Translate a single instruction. Delayed branches are handled specially
1.108 + * by translating both branch and delayed instruction as a single unit (as
1.109 + *
1.110 + *
1.111 + * @return true if the instruction marks the end of a basic block
1.112 + * (eg a branch or
1.113 + */
1.114 +uint32_t sh4_x86_translate_instruction( uint32_t pc )
1.115 +{
1.116 + uint16_t ir = 0;
1.117 +
1.118 + switch( (ir&0xF000) >> 12 ) {
1.119 + case 0x0:
1.120 + switch( ir&0xF ) {
1.121 + case 0x2:
1.122 + switch( (ir&0x80) >> 7 ) {
1.123 + case 0x0:
1.124 + switch( (ir&0x70) >> 4 ) {
1.125 + case 0x0:
1.126 + { /* STC SR, Rn */
1.127 + uint32_t Rn = ((ir>>8)&0xF);
1.128 + /* TODO */
1.129 + }
1.130 + break;
1.131 + case 0x1:
1.132 + { /* STC GBR, Rn */
1.133 + uint32_t Rn = ((ir>>8)&0xF);
1.134 + load_spreg( R_EAX, R_GBR );
1.135 + store_reg( R_EAX, Rn );
1.136 + }
1.137 + break;
1.138 + case 0x2:
1.139 + { /* STC VBR, Rn */
1.140 + uint32_t Rn = ((ir>>8)&0xF);
1.141 + load_spreg( R_EAX, R_VBR );
1.142 + store_reg( R_EAX, Rn );
1.143 + }
1.144 + break;
1.145 + case 0x3:
1.146 + { /* STC SSR, Rn */
1.147 + uint32_t Rn = ((ir>>8)&0xF);
1.148 + load_spreg( R_EAX, R_SSR );
1.149 + store_reg( R_EAX, Rn );
1.150 + }
1.151 + break;
1.152 + case 0x4:
1.153 + { /* STC SPC, Rn */
1.154 + uint32_t Rn = ((ir>>8)&0xF);
1.155 + load_spreg( R_EAX, R_SPC );
1.156 + store_reg( R_EAX, Rn );
1.157 + }
1.158 + break;
1.159 + default:
1.160 + UNDEF();
1.161 + break;
1.162 + }
1.163 + break;
1.164 + case 0x1:
1.165 + { /* STC Rm_BANK, Rn */
1.166 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
1.167 + /* TODO */
1.168 + }
1.169 + break;
1.170 + }
1.171 + break;
1.172 + case 0x3:
1.173 + switch( (ir&0xF0) >> 4 ) {
1.174 + case 0x0:
1.175 + { /* BSRF Rn */
1.176 + uint32_t Rn = ((ir>>8)&0xF);
1.177 + }
1.178 + break;
1.179 + case 0x2:
1.180 + { /* BRAF Rn */
1.181 + uint32_t Rn = ((ir>>8)&0xF);
1.182 + }
1.183 + break;
1.184 + case 0x8:
1.185 + { /* PREF @Rn */
1.186 + uint32_t Rn = ((ir>>8)&0xF);
1.187 + }
1.188 + break;
1.189 + case 0x9:
1.190 + { /* OCBI @Rn */
1.191 + uint32_t Rn = ((ir>>8)&0xF);
1.192 + }
1.193 + break;
1.194 + case 0xA:
1.195 + { /* OCBP @Rn */
1.196 + uint32_t Rn = ((ir>>8)&0xF);
1.197 + }
1.198 + break;
1.199 + case 0xB:
1.200 + { /* OCBWB @Rn */
1.201 + uint32_t Rn = ((ir>>8)&0xF);
1.202 + }
1.203 + break;
1.204 + case 0xC:
1.205 + { /* MOVCA.L R0, @Rn */
1.206 + uint32_t Rn = ((ir>>8)&0xF);
1.207 + }
1.208 + break;
1.209 + default:
1.210 + UNDEF();
1.211 + break;
1.212 + }
1.213 + break;
1.214 + case 0x4:
1.215 + { /* MOV.B Rm, @(R0, Rn) */
1.216 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.217 + load_reg( R_EAX, 0 );
1.218 + load_reg( R_ECX, Rn );
1.219 + ADD_r32_r32( R_EAX, R_ECX );
1.220 + load_reg( R_EAX, Rm );
1.221 + MEM_WRITE_BYTE( R_ECX, R_EAX );
1.222 + }
1.223 + break;
1.224 + case 0x5:
1.225 + { /* MOV.W Rm, @(R0, Rn) */
1.226 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.227 + }
1.228 + break;
1.229 + case 0x6:
1.230 + { /* MOV.L Rm, @(R0, Rn) */
1.231 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.232 + }
1.233 + break;
1.234 + case 0x7:
1.235 + { /* MUL.L Rm, Rn */
1.236 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.237 + }
1.238 + break;
1.239 + case 0x8:
1.240 + switch( (ir&0xFF0) >> 4 ) {
1.241 + case 0x0:
1.242 + { /* CLRT */
1.243 + }
1.244 + break;
1.245 + case 0x1:
1.246 + { /* SETT */
1.247 + }
1.248 + break;
1.249 + case 0x2:
1.250 + { /* CLRMAC */
1.251 + }
1.252 + break;
1.253 + case 0x3:
1.254 + { /* LDTLB */
1.255 + }
1.256 + break;
1.257 + case 0x4:
1.258 + { /* CLRS */
1.259 + }
1.260 + break;
1.261 + case 0x5:
1.262 + { /* SETS */
1.263 + }
1.264 + break;
1.265 + default:
1.266 + UNDEF();
1.267 + break;
1.268 + }
1.269 + break;
1.270 + case 0x9:
1.271 + switch( (ir&0xF0) >> 4 ) {
1.272 + case 0x0:
1.273 + { /* NOP */
1.274 + /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
1.275 + }
1.276 + break;
1.277 + case 0x1:
1.278 + { /* DIV0U */
1.279 + }
1.280 + break;
1.281 + case 0x2:
1.282 + { /* MOVT Rn */
1.283 + uint32_t Rn = ((ir>>8)&0xF);
1.284 + load_spreg( R_EAX, R_T );
1.285 + store_reg( R_EAX, Rn );
1.286 + }
1.287 + break;
1.288 + default:
1.289 + UNDEF();
1.290 + break;
1.291 + }
1.292 + break;
1.293 + case 0xA:
1.294 + switch( (ir&0xF0) >> 4 ) {
1.295 + case 0x0:
1.296 + { /* STS MACH, Rn */
1.297 + uint32_t Rn = ((ir>>8)&0xF);
1.298 + load_spreg( R_EAX, R_MACH );
1.299 + store_reg( R_EAX, Rn );
1.300 + }
1.301 + break;
1.302 + case 0x1:
1.303 + { /* STS MACL, Rn */
1.304 + uint32_t Rn = ((ir>>8)&0xF);
1.305 + load_spreg( R_EAX, R_MACL );
1.306 + store_reg( R_EAX, Rn );
1.307 + }
1.308 + break;
1.309 + case 0x2:
1.310 + { /* STS PR, Rn */
1.311 + uint32_t Rn = ((ir>>8)&0xF);
1.312 + load_spreg( R_EAX, R_PR );
1.313 + store_reg( R_EAX, Rn );
1.314 + }
1.315 + break;
1.316 + case 0x3:
1.317 + { /* STC SGR, Rn */
1.318 + uint32_t Rn = ((ir>>8)&0xF);
1.319 + load_spreg( R_EAX, R_SGR );
1.320 + store_reg( R_EAX, Rn );
1.321 + }
1.322 + break;
1.323 + case 0x5:
1.324 + { /* STS FPUL, Rn */
1.325 + uint32_t Rn = ((ir>>8)&0xF);
1.326 + load_spreg( R_EAX, R_FPUL );
1.327 + store_reg( R_EAX, Rn );
1.328 + }
1.329 + break;
1.330 + case 0x6:
1.331 + { /* STS FPSCR, Rn */
1.332 + uint32_t Rn = ((ir>>8)&0xF);
1.333 + load_spreg( R_EAX, R_FPSCR );
1.334 + store_reg( R_EAX, Rn );
1.335 + }
1.336 + break;
1.337 + case 0xF:
1.338 + { /* STC DBR, Rn */
1.339 + uint32_t Rn = ((ir>>8)&0xF);
1.340 + load_spreg( R_EAX, R_DBR );
1.341 + store_reg( R_EAX, Rn );
1.342 + }
1.343 + break;
1.344 + default:
1.345 + UNDEF();
1.346 + break;
1.347 + }
1.348 + break;
1.349 + case 0xB:
1.350 + switch( (ir&0xFF0) >> 4 ) {
1.351 + case 0x0:
1.352 + { /* RTS */
1.353 + }
1.354 + break;
1.355 + case 0x1:
1.356 + { /* SLEEP */
1.357 + }
1.358 + break;
1.359 + case 0x2:
1.360 + { /* RTE */
1.361 + }
1.362 + break;
1.363 + default:
1.364 + UNDEF();
1.365 + break;
1.366 + }
1.367 + break;
1.368 + case 0xC:
1.369 + { /* MOV.B @(R0, Rm), Rn */
1.370 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.371 + load_reg( R_EAX, 0 );
1.372 + load_reg( R_ECX, Rm );
1.373 + ADD_r32_r32( R_EAX, R_ECX );
1.374 + MEM_READ_BYTE( R_ECX, R_EAX );
1.375 + store_reg( R_EAX, Rn );
1.376 + }
1.377 + break;
1.378 + case 0xD:
1.379 + { /* MOV.W @(R0, Rm), Rn */
1.380 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.381 + }
1.382 + break;
1.383 + case 0xE:
1.384 + { /* MOV.L @(R0, Rm), Rn */
1.385 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.386 + }
1.387 + break;
1.388 + case 0xF:
1.389 + { /* MAC.L @Rm+, @Rn+ */
1.390 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.391 + }
1.392 + break;
1.393 + default:
1.394 + UNDEF();
1.395 + break;
1.396 + }
1.397 + break;
1.398 + case 0x1:
1.399 + { /* MOV.L Rm, @(disp, Rn) */
1.400 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1.401 + }
1.402 + break;
1.403 + case 0x2:
1.404 + switch( ir&0xF ) {
1.405 + case 0x0:
1.406 + { /* MOV.B Rm, @Rn */
1.407 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.408 + load_reg( R_EAX, Rm );
1.409 + load_reg( R_ECX, Rn );
1.410 + MEM_WRITE_BYTE( R_ECX, R_EAX );
1.411 + }
1.412 + break;
1.413 + case 0x1:
1.414 + { /* MOV.W Rm, @Rn */
1.415 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.416 + }
1.417 + break;
1.418 + case 0x2:
1.419 + { /* MOV.L Rm, @Rn */
1.420 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.421 + }
1.422 + break;
1.423 + case 0x4:
1.424 + { /* MOV.B Rm, @-Rn */
1.425 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.426 + load_reg( R_EAX, Rm );
1.427 + load_reg( R_ECX, Rn );
1.428 + ADD_imm8s_r32( -1, Rn );
1.429 + store_reg( R_ECX, Rn );
1.430 + MEM_WRITE_BYTE( R_ECX, R_EAX );
1.431 + }
1.432 + break;
1.433 + case 0x5:
1.434 + { /* MOV.W Rm, @-Rn */
1.435 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.436 + }
1.437 + break;
1.438 + case 0x6:
1.439 + { /* MOV.L Rm, @-Rn */
1.440 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.441 + }
1.442 + break;
1.443 + case 0x7:
1.444 + { /* DIV0S Rm, Rn */
1.445 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.446 + }
1.447 + break;
1.448 + case 0x8:
1.449 + { /* TST Rm, Rn */
1.450 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.451 + }
1.452 + break;
1.453 + case 0x9:
1.454 + { /* AND Rm, Rn */
1.455 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.456 + load_reg( R_EAX, Rm );
1.457 + load_reg( R_ECX, Rn );
1.458 + AND_r32_r32( R_EAX, R_ECX );
1.459 + store_reg( R_ECX, Rn );
1.460 + }
1.461 + break;
1.462 + case 0xA:
1.463 + { /* XOR Rm, Rn */
1.464 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.465 + load_reg( R_EAX, Rm );
1.466 + load_reg( R_ECX, Rn );
1.467 + XOR_r32_r32( R_EAX, R_ECX );
1.468 + store_reg( R_ECX, Rn );
1.469 + }
1.470 + break;
1.471 + case 0xB:
1.472 + { /* OR Rm, Rn */
1.473 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.474 + load_reg( R_EAX, Rm );
1.475 + load_reg( R_ECX, Rn );
1.476 + OR_r32_r32( R_EAX, R_ECX );
1.477 + store_reg( R_ECX, Rn );
1.478 + }
1.479 + break;
1.480 + case 0xC:
1.481 + { /* CMP/STR Rm, Rn */
1.482 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.483 + }
1.484 + break;
1.485 + case 0xD:
1.486 + { /* XTRCT Rm, Rn */
1.487 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.488 + }
1.489 + break;
1.490 + case 0xE:
1.491 + { /* MULU.W Rm, Rn */
1.492 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.493 + }
1.494 + break;
1.495 + case 0xF:
1.496 + { /* MULS.W Rm, Rn */
1.497 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.498 + }
1.499 + break;
1.500 + default:
1.501 + UNDEF();
1.502 + break;
1.503 + }
1.504 + break;
1.505 + case 0x3:
1.506 + switch( ir&0xF ) {
1.507 + case 0x0:
1.508 + { /* CMP/EQ Rm, Rn */
1.509 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.510 + load_reg( R_EAX, Rm );
1.511 + load_reg( R_ECX, Rn );
1.512 + CMP_r32_r32( R_EAX, R_ECX );
1.513 + SETE_t();
1.514 + }
1.515 + break;
1.516 + case 0x2:
1.517 + { /* CMP/HS Rm, Rn */
1.518 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.519 + load_reg( R_EAX, Rm );
1.520 + load_reg( R_ECX, Rn );
1.521 + CMP_r32_r32( R_EAX, R_ECX );
1.522 + SETAE_t();
1.523 + }
1.524 + break;
1.525 + case 0x3:
1.526 + { /* CMP/GE Rm, Rn */
1.527 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.528 + load_reg( R_EAX, Rm );
1.529 + load_reg( R_ECX, Rn );
1.530 + CMP_r32_r32( R_EAX, R_ECX );
1.531 + SETGE_t();
1.532 + }
1.533 + break;
1.534 + case 0x4:
1.535 + { /* DIV1 Rm, Rn */
1.536 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.537 + }
1.538 + break;
1.539 + case 0x5:
1.540 + { /* DMULU.L Rm, Rn */
1.541 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.542 + }
1.543 + break;
1.544 + case 0x6:
1.545 + { /* CMP/HI Rm, Rn */
1.546 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.547 + load_reg( R_EAX, Rm );
1.548 + load_reg( R_ECX, Rn );
1.549 + CMP_r32_r32( R_EAX, R_ECX );
1.550 + SETA_t();
1.551 + }
1.552 + break;
1.553 + case 0x7:
1.554 + { /* CMP/GT Rm, Rn */
1.555 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.556 + load_reg( R_EAX, Rm );
1.557 + load_reg( R_ECX, Rn );
1.558 + CMP_r32_r32( R_EAX, R_ECX );
1.559 + SETG_t();
1.560 + }
1.561 + break;
1.562 + case 0x8:
1.563 + { /* SUB Rm, Rn */
1.564 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.565 + load_reg( R_EAX, Rm );
1.566 + load_reg( R_ECX, Rn );
1.567 + SUB_r32_r32( R_EAX, R_ECX );
1.568 + store_reg( R_ECX, Rn );
1.569 + }
1.570 + break;
1.571 + case 0xA:
1.572 + { /* SUBC Rm, Rn */
1.573 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.574 + load_reg( R_EAX, Rm );
1.575 + load_reg( R_ECX, Rn );
1.576 + LDC_t();
1.577 + SBB_r32_r32( R_EAX, R_ECX );
1.578 + store_reg( R_ECX, Rn );
1.579 + }
1.580 + break;
1.581 + case 0xB:
1.582 + { /* SUBV Rm, Rn */
1.583 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.584 + load_reg( R_EAX, Rm );
1.585 + load_reg( R_ECX, Rn );
1.586 + SUB_r32_r32( R_EAX, R_ECX );
1.587 + store_reg( R_ECX, Rn );
1.588 + SETO_t();
1.589 + }
1.590 + break;
1.591 + case 0xC:
1.592 + { /* ADD Rm, Rn */
1.593 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.594 + load_reg( R_EAX, Rm );
1.595 + load_reg( R_ECX, Rn );
1.596 + ADD_r32_r32( R_EAX, R_ECX );
1.597 + store_reg( R_ECX, Rn );
1.598 + }
1.599 + break;
1.600 + case 0xD:
1.601 + { /* DMULS.L Rm, Rn */
1.602 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.603 + }
1.604 + break;
1.605 + case 0xE:
1.606 + { /* ADDC Rm, Rn */
1.607 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.608 + load_reg( R_EAX, Rm );
1.609 + load_reg( R_ECX, Rn );
1.610 + LDC_t();
1.611 + ADC_r32_r32( R_EAX, R_ECX );
1.612 + store_reg( R_ECX, Rn );
1.613 + SETC_t();
1.614 + }
1.615 + break;
1.616 + case 0xF:
1.617 + { /* ADDV Rm, Rn */
1.618 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.619 + load_reg( R_EAX, Rm );
1.620 + load_reg( R_ECX, Rn );
1.621 + ADD_r32_r32( R_EAX, R_ECX );
1.622 + store_reg( R_ECX, Rn );
1.623 + SETO_t();
1.624 + }
1.625 + break;
1.626 + default:
1.627 + UNDEF();
1.628 + break;
1.629 + }
1.630 + break;
1.631 + case 0x4:
1.632 + switch( ir&0xF ) {
1.633 + case 0x0:
1.634 + switch( (ir&0xF0) >> 4 ) {
1.635 + case 0x0:
1.636 + { /* SHLL Rn */
1.637 + uint32_t Rn = ((ir>>8)&0xF);
1.638 + load_reg( R_EAX, Rn );
1.639 + SHL1_r32( R_EAX );
1.640 + store_reg( R_EAX, Rn );
1.641 + }
1.642 + break;
1.643 + case 0x1:
1.644 + { /* DT Rn */
1.645 + uint32_t Rn = ((ir>>8)&0xF);
1.646 + load_reg( R_EAX, Rn );
1.647 + ADD_imm8s_r32( -1, Rn );
1.648 + store_reg( R_EAX, Rn );
1.649 + SETE_t();
1.650 + }
1.651 + break;
1.652 + case 0x2:
1.653 + { /* SHAL Rn */
1.654 + uint32_t Rn = ((ir>>8)&0xF);
1.655 + load_reg( R_EAX, Rn );
1.656 + SHL1_r32( R_EAX );
1.657 + store_reg( R_EAX, Rn );
1.658 + }
1.659 + break;
1.660 + default:
1.661 + UNDEF();
1.662 + break;
1.663 + }
1.664 + break;
1.665 + case 0x1:
1.666 + switch( (ir&0xF0) >> 4 ) {
1.667 + case 0x0:
1.668 + { /* SHLR Rn */
1.669 + uint32_t Rn = ((ir>>8)&0xF);
1.670 + load_reg( R_EAX, Rn );
1.671 + SHR1_r32( R_EAX );
1.672 + store_reg( R_EAX, Rn );
1.673 + }
1.674 + break;
1.675 + case 0x1:
1.676 + { /* CMP/PZ Rn */
1.677 + uint32_t Rn = ((ir>>8)&0xF);
1.678 + load_reg( R_EAX, Rn );
1.679 + CMP_imm8s_r32( 0, R_EAX );
1.680 + SETGE_t();
1.681 + }
1.682 + break;
1.683 + case 0x2:
1.684 + { /* SHAR Rn */
1.685 + uint32_t Rn = ((ir>>8)&0xF);
1.686 + load_reg( R_EAX, Rn );
1.687 + SAR1_r32( R_EAX );
1.688 + store_reg( R_EAX, Rn );
1.689 + }
1.690 + break;
1.691 + default:
1.692 + UNDEF();
1.693 + break;
1.694 + }
1.695 + break;
1.696 + case 0x2:
1.697 + switch( (ir&0xF0) >> 4 ) {
1.698 + case 0x0:
1.699 + { /* STS.L MACH, @-Rn */
1.700 + uint32_t Rn = ((ir>>8)&0xF);
1.701 + load_reg( R_ECX, Rn );
1.702 + ADD_imm8s_r32( -4, Rn );
1.703 + store_reg( R_ECX, Rn );
1.704 + load_spreg( R_EAX, R_MACH );
1.705 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.706 + }
1.707 + break;
1.708 + case 0x1:
1.709 + { /* STS.L MACL, @-Rn */
1.710 + uint32_t Rn = ((ir>>8)&0xF);
1.711 + load_reg( R_ECX, Rn );
1.712 + ADD_imm8s_r32( -4, Rn );
1.713 + store_reg( R_ECX, Rn );
1.714 + load_spreg( R_EAX, R_MACL );
1.715 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.716 + }
1.717 + break;
1.718 + case 0x2:
1.719 + { /* STS.L PR, @-Rn */
1.720 + uint32_t Rn = ((ir>>8)&0xF);
1.721 + load_reg( R_ECX, Rn );
1.722 + ADD_imm8s_r32( -4, Rn );
1.723 + store_reg( R_ECX, Rn );
1.724 + load_spreg( R_EAX, R_PR );
1.725 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.726 + }
1.727 + break;
1.728 + case 0x3:
1.729 + { /* STC.L SGR, @-Rn */
1.730 + uint32_t Rn = ((ir>>8)&0xF);
1.731 + load_reg( R_ECX, Rn );
1.732 + ADD_imm8s_r32( -4, Rn );
1.733 + store_reg( R_ECX, Rn );
1.734 + load_spreg( R_EAX, R_SGR );
1.735 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.736 + }
1.737 + break;
1.738 + case 0x5:
1.739 + { /* STS.L FPUL, @-Rn */
1.740 + uint32_t Rn = ((ir>>8)&0xF);
1.741 + load_reg( R_ECX, Rn );
1.742 + ADD_imm8s_r32( -4, Rn );
1.743 + store_reg( R_ECX, Rn );
1.744 + load_spreg( R_EAX, R_FPUL );
1.745 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.746 + }
1.747 + break;
1.748 + case 0x6:
1.749 + { /* STS.L FPSCR, @-Rn */
1.750 + uint32_t Rn = ((ir>>8)&0xF);
1.751 + load_reg( R_ECX, Rn );
1.752 + ADD_imm8s_r32( -4, Rn );
1.753 + store_reg( R_ECX, Rn );
1.754 + load_spreg( R_EAX, R_FPSCR );
1.755 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.756 + }
1.757 + break;
1.758 + case 0xF:
1.759 + { /* STC.L DBR, @-Rn */
1.760 + uint32_t Rn = ((ir>>8)&0xF);
1.761 + load_reg( R_ECX, Rn );
1.762 + ADD_imm8s_r32( -4, Rn );
1.763 + store_reg( R_ECX, Rn );
1.764 + load_spreg( R_EAX, R_DBR );
1.765 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.766 + }
1.767 + break;
1.768 + default:
1.769 + UNDEF();
1.770 + break;
1.771 + }
1.772 + break;
1.773 + case 0x3:
1.774 + switch( (ir&0x80) >> 7 ) {
1.775 + case 0x0:
1.776 + switch( (ir&0x70) >> 4 ) {
1.777 + case 0x0:
1.778 + { /* STC.L SR, @-Rn */
1.779 + uint32_t Rn = ((ir>>8)&0xF);
1.780 + /* TODO */
1.781 + }
1.782 + break;
1.783 + case 0x1:
1.784 + { /* STC.L GBR, @-Rn */
1.785 + uint32_t Rn = ((ir>>8)&0xF);
1.786 + load_reg( R_ECX, Rn );
1.787 + ADD_imm8s_r32( -4, Rn );
1.788 + store_reg( R_ECX, Rn );
1.789 + load_spreg( R_EAX, R_GBR );
1.790 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.791 + }
1.792 + break;
1.793 + case 0x2:
1.794 + { /* STC.L VBR, @-Rn */
1.795 + uint32_t Rn = ((ir>>8)&0xF);
1.796 + load_reg( R_ECX, Rn );
1.797 + ADD_imm8s_r32( -4, Rn );
1.798 + store_reg( R_ECX, Rn );
1.799 + load_spreg( R_EAX, R_VBR );
1.800 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.801 + }
1.802 + break;
1.803 + case 0x3:
1.804 + { /* STC.L SSR, @-Rn */
1.805 + uint32_t Rn = ((ir>>8)&0xF);
1.806 + load_reg( R_ECX, Rn );
1.807 + ADD_imm8s_r32( -4, Rn );
1.808 + store_reg( R_ECX, Rn );
1.809 + load_spreg( R_EAX, R_SSR );
1.810 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.811 + }
1.812 + break;
1.813 + case 0x4:
1.814 + { /* STC.L SPC, @-Rn */
1.815 + uint32_t Rn = ((ir>>8)&0xF);
1.816 + load_reg( R_ECX, Rn );
1.817 + ADD_imm8s_r32( -4, Rn );
1.818 + store_reg( R_ECX, Rn );
1.819 + load_spreg( R_EAX, R_SPC );
1.820 + MEM_WRITE_LONG( R_ECX, R_EAX );
1.821 + }
1.822 + break;
1.823 + default:
1.824 + UNDEF();
1.825 + break;
1.826 + }
1.827 + break;
1.828 + case 0x1:
1.829 + { /* STC.L Rm_BANK, @-Rn */
1.830 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
1.831 + }
1.832 + break;
1.833 + }
1.834 + break;
1.835 + case 0x4:
1.836 + switch( (ir&0xF0) >> 4 ) {
1.837 + case 0x0:
1.838 + { /* ROTL Rn */
1.839 + uint32_t Rn = ((ir>>8)&0xF);
1.840 + load_reg( R_EAX, Rn );
1.841 + ROL1_r32( R_EAX );
1.842 + store_reg( R_EAX, Rn );
1.843 + SETC_t();
1.844 + }
1.845 + break;
1.846 + case 0x2:
1.847 + { /* ROTCL Rn */
1.848 + uint32_t Rn = ((ir>>8)&0xF);
1.849 + load_reg( R_EAX, Rn );
1.850 + LDC_t();
1.851 + RCL1_r32( R_EAX );
1.852 + store_reg( R_EAX, Rn );
1.853 + SETC_t();
1.854 + }
1.855 + break;
1.856 + default:
1.857 + UNDEF();
1.858 + break;
1.859 + }
1.860 + break;
1.861 + case 0x5:
1.862 + switch( (ir&0xF0) >> 4 ) {
1.863 + case 0x0:
1.864 + { /* ROTR Rn */
1.865 + uint32_t Rn = ((ir>>8)&0xF);
1.866 + load_reg( R_EAX, Rn );
1.867 + ROR1_r32( R_EAX );
1.868 + store_reg( R_EAX, Rn );
1.869 + SETC_t();
1.870 + }
1.871 + break;
1.872 + case 0x1:
1.873 + { /* CMP/PL Rn */
1.874 + uint32_t Rn = ((ir>>8)&0xF);
1.875 + load_reg( R_EAX, Rn );
1.876 + CMP_imm8s_r32( 0, R_EAX );
1.877 + SETG_t();
1.878 + }
1.879 + break;
1.880 + case 0x2:
1.881 + { /* ROTCR Rn */
1.882 + uint32_t Rn = ((ir>>8)&0xF);
1.883 + load_reg( R_EAX, Rn );
1.884 + LDC_t();
1.885 + RCR1_r32( R_EAX );
1.886 + store_reg( R_EAX, Rn );
1.887 + SETC_t();
1.888 + }
1.889 + break;
1.890 + default:
1.891 + UNDEF();
1.892 + break;
1.893 + }
1.894 + break;
1.895 + case 0x6:
1.896 + switch( (ir&0xF0) >> 4 ) {
1.897 + case 0x0:
1.898 + { /* LDS.L @Rm+, MACH */
1.899 + uint32_t Rm = ((ir>>8)&0xF);
1.900 + load_reg( R_EAX, Rm );
1.901 + MOV_r32_r32( R_EAX, R_ECX );
1.902 + ADD_imm8s_r32( 4, R_EAX );
1.903 + store_reg( R_EAX, Rm );
1.904 + MEM_READ_LONG( R_ECX, R_EAX );
1.905 + store_spreg( R_EAX, R_MACH );
1.906 + }
1.907 + break;
1.908 + case 0x1:
1.909 + { /* LDS.L @Rm+, MACL */
1.910 + uint32_t Rm = ((ir>>8)&0xF);
1.911 + load_reg( R_EAX, Rm );
1.912 + MOV_r32_r32( R_EAX, R_ECX );
1.913 + ADD_imm8s_r32( 4, R_EAX );
1.914 + store_reg( R_EAX, Rm );
1.915 + MEM_READ_LONG( R_ECX, R_EAX );
1.916 + store_spreg( R_EAX, R_MACL );
1.917 + }
1.918 + break;
1.919 + case 0x2:
1.920 + { /* LDS.L @Rm+, PR */
1.921 + uint32_t Rm = ((ir>>8)&0xF);
1.922 + load_reg( R_EAX, Rm );
1.923 + MOV_r32_r32( R_EAX, R_ECX );
1.924 + ADD_imm8s_r32( 4, R_EAX );
1.925 + store_reg( R_EAX, Rm );
1.926 + MEM_READ_LONG( R_ECX, R_EAX );
1.927 + store_spreg( R_EAX, R_PR );
1.928 + }
1.929 + break;
1.930 + case 0x3:
1.931 + { /* LDC.L @Rm+, SGR */
1.932 + uint32_t Rm = ((ir>>8)&0xF);
1.933 + load_reg( R_EAX, Rm );
1.934 + MOV_r32_r32( R_EAX, R_ECX );
1.935 + ADD_imm8s_r32( 4, R_EAX );
1.936 + store_reg( R_EAX, Rm );
1.937 + MEM_READ_LONG( R_ECX, R_EAX );
1.938 + store_spreg( R_EAX, R_SGR );
1.939 + }
1.940 + break;
1.941 + case 0x5:
1.942 + { /* LDS.L @Rm+, FPUL */
1.943 + uint32_t Rm = ((ir>>8)&0xF);
1.944 + load_reg( R_EAX, Rm );
1.945 + MOV_r32_r32( R_EAX, R_ECX );
1.946 + ADD_imm8s_r32( 4, R_EAX );
1.947 + store_reg( R_EAX, Rm );
1.948 + MEM_READ_LONG( R_ECX, R_EAX );
1.949 + store_spreg( R_EAX, R_FPUL );
1.950 + }
1.951 + break;
1.952 + case 0x6:
1.953 + { /* LDS.L @Rm+, FPSCR */
1.954 + uint32_t Rm = ((ir>>8)&0xF);
1.955 + load_reg( R_EAX, Rm );
1.956 + MOV_r32_r32( R_EAX, R_ECX );
1.957 + ADD_imm8s_r32( 4, R_EAX );
1.958 + store_reg( R_EAX, Rm );
1.959 + MEM_READ_LONG( R_ECX, R_EAX );
1.960 + store_spreg( R_EAX, R_FPSCR );
1.961 + }
1.962 + break;
1.963 + case 0xF:
1.964 + { /* LDC.L @Rm+, DBR */
1.965 + uint32_t Rm = ((ir>>8)&0xF);
1.966 + load_reg( R_EAX, Rm );
1.967 + MOV_r32_r32( R_EAX, R_ECX );
1.968 + ADD_imm8s_r32( 4, R_EAX );
1.969 + store_reg( R_EAX, Rm );
1.970 + MEM_READ_LONG( R_ECX, R_EAX );
1.971 + store_spreg( R_EAX, R_DBR );
1.972 + }
1.973 + break;
1.974 + default:
1.975 + UNDEF();
1.976 + break;
1.977 + }
1.978 + break;
1.979 + case 0x7:
1.980 + switch( (ir&0x80) >> 7 ) {
1.981 + case 0x0:
1.982 + switch( (ir&0x70) >> 4 ) {
1.983 + case 0x0:
1.984 + { /* LDC.L @Rm+, SR */
1.985 + uint32_t Rm = ((ir>>8)&0xF);
1.986 + }
1.987 + break;
1.988 + case 0x1:
1.989 + { /* LDC.L @Rm+, GBR */
1.990 + uint32_t Rm = ((ir>>8)&0xF);
1.991 + load_reg( R_EAX, Rm );
1.992 + MOV_r32_r32( R_EAX, R_ECX );
1.993 + ADD_imm8s_r32( 4, R_EAX );
1.994 + store_reg( R_EAX, Rm );
1.995 + MEM_READ_LONG( R_ECX, R_EAX );
1.996 + store_spreg( R_EAX, R_GBR );
1.997 + }
1.998 + break;
1.999 + case 0x2:
1.1000 + { /* LDC.L @Rm+, VBR */
1.1001 + uint32_t Rm = ((ir>>8)&0xF);
1.1002 + load_reg( R_EAX, Rm );
1.1003 + MOV_r32_r32( R_EAX, R_ECX );
1.1004 + ADD_imm8s_r32( 4, R_EAX );
1.1005 + store_reg( R_EAX, Rm );
1.1006 + MEM_READ_LONG( R_ECX, R_EAX );
1.1007 + store_spreg( R_EAX, R_VBR );
1.1008 + }
1.1009 + break;
1.1010 + case 0x3:
1.1011 + { /* LDC.L @Rm+, SSR */
1.1012 + uint32_t Rm = ((ir>>8)&0xF);
1.1013 + load_reg( R_EAX, Rm );
1.1014 + MOV_r32_r32( R_EAX, R_ECX );
1.1015 + ADD_imm8s_r32( 4, R_EAX );
1.1016 + store_reg( R_EAX, Rm );
1.1017 + MEM_READ_LONG( R_ECX, R_EAX );
1.1018 + store_spreg( R_EAX, R_SSR );
1.1019 + }
1.1020 + break;
1.1021 + case 0x4:
1.1022 + { /* LDC.L @Rm+, SPC */
1.1023 + uint32_t Rm = ((ir>>8)&0xF);
1.1024 + load_reg( R_EAX, Rm );
1.1025 + MOV_r32_r32( R_EAX, R_ECX );
1.1026 + ADD_imm8s_r32( 4, R_EAX );
1.1027 + store_reg( R_EAX, Rm );
1.1028 + MEM_READ_LONG( R_ECX, R_EAX );
1.1029 + store_spreg( R_EAX, R_SPC );
1.1030 + }
1.1031 + break;
1.1032 + default:
1.1033 + UNDEF();
1.1034 + break;
1.1035 + }
1.1036 + break;
1.1037 + case 0x1:
1.1038 + { /* LDC.L @Rm+, Rn_BANK */
1.1039 + uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1.1040 + }
1.1041 + break;
1.1042 + }
1.1043 + break;
1.1044 + case 0x8:
1.1045 + switch( (ir&0xF0) >> 4 ) {
1.1046 + case 0x0:
1.1047 + { /* SHLL2 Rn */
1.1048 + uint32_t Rn = ((ir>>8)&0xF);
1.1049 + load_reg( R_EAX, Rn );
1.1050 + SHL_imm8_r32( 2, R_EAX );
1.1051 + store_reg( R_EAX, Rn );
1.1052 + }
1.1053 + break;
1.1054 + case 0x1:
1.1055 + { /* SHLL8 Rn */
1.1056 + uint32_t Rn = ((ir>>8)&0xF);
1.1057 + load_reg( R_EAX, Rn );
1.1058 + SHL_imm8_r32( 8, R_EAX );
1.1059 + store_reg( R_EAX, Rn );
1.1060 + }
1.1061 + break;
1.1062 + case 0x2:
1.1063 + { /* SHLL16 Rn */
1.1064 + uint32_t Rn = ((ir>>8)&0xF);
1.1065 + load_reg( R_EAX, Rn );
1.1066 + SHL_imm8_r32( 16, R_EAX );
1.1067 + store_reg( R_EAX, Rn );
1.1068 + }
1.1069 + break;
1.1070 + default:
1.1071 + UNDEF();
1.1072 + break;
1.1073 + }
1.1074 + break;
1.1075 + case 0x9:
1.1076 + switch( (ir&0xF0) >> 4 ) {
1.1077 + case 0x0:
1.1078 + { /* SHLR2 Rn */
1.1079 + uint32_t Rn = ((ir>>8)&0xF);
1.1080 + load_reg( R_EAX, Rn );
1.1081 + SHR_imm8_r32( 2, R_EAX );
1.1082 + store_reg( R_EAX, Rn );
1.1083 + }
1.1084 + break;
1.1085 + case 0x1:
1.1086 + { /* SHLR8 Rn */
1.1087 + uint32_t Rn = ((ir>>8)&0xF);
1.1088 + load_reg( R_EAX, Rn );
1.1089 + SHR_imm8_r32( 8, R_EAX );
1.1090 + store_reg( R_EAX, Rn );
1.1091 + }
1.1092 + break;
1.1093 + case 0x2:
1.1094 + { /* SHLR16 Rn */
1.1095 + uint32_t Rn = ((ir>>8)&0xF);
1.1096 + load_reg( R_EAX, Rn );
1.1097 + SHR_imm8_r32( 16, R_EAX );
1.1098 + store_reg( R_EAX, Rn );
1.1099 + }
1.1100 + break;
1.1101 + default:
1.1102 + UNDEF();
1.1103 + break;
1.1104 + }
1.1105 + break;
1.1106 + case 0xA:
1.1107 + switch( (ir&0xF0) >> 4 ) {
1.1108 + case 0x0:
1.1109 + { /* LDS Rm, MACH */
1.1110 + uint32_t Rm = ((ir>>8)&0xF);
1.1111 + load_reg( R_EAX, Rm );
1.1112 + store_spreg( R_EAX, R_MACH );
1.1113 + }
1.1114 + break;
1.1115 + case 0x1:
1.1116 + { /* LDS Rm, MACL */
1.1117 + uint32_t Rm = ((ir>>8)&0xF);
1.1118 + load_reg( R_EAX, Rm );
1.1119 + store_spreg( R_EAX, R_MACL );
1.1120 + }
1.1121 + break;
1.1122 + case 0x2:
1.1123 + { /* LDS Rm, PR */
1.1124 + uint32_t Rm = ((ir>>8)&0xF);
1.1125 + load_reg( R_EAX, Rm );
1.1126 + store_spreg( R_EAX, R_PR );
1.1127 + }
1.1128 + break;
1.1129 + case 0x3:
1.1130 + { /* LDC Rm, SGR */
1.1131 + uint32_t Rm = ((ir>>8)&0xF);
1.1132 + load_reg( R_EAX, Rm );
1.1133 + store_spreg( R_EAX, R_SGR );
1.1134 + }
1.1135 + break;
1.1136 + case 0x5:
1.1137 + { /* LDS Rm, FPUL */
1.1138 + uint32_t Rm = ((ir>>8)&0xF);
1.1139 + load_reg( R_EAX, Rm );
1.1140 + store_spreg( R_EAX, R_FPUL );
1.1141 + }
1.1142 + break;
1.1143 + case 0x6:
1.1144 + { /* LDS Rm, FPSCR */
1.1145 + uint32_t Rm = ((ir>>8)&0xF);
1.1146 + load_reg( R_EAX, Rm );
1.1147 + store_spreg( R_EAX, R_FPSCR );
1.1148 + }
1.1149 + break;
1.1150 + case 0xF:
1.1151 + { /* LDC Rm, DBR */
1.1152 + uint32_t Rm = ((ir>>8)&0xF);
1.1153 + load_reg( R_EAX, Rm );
1.1154 + store_spreg( R_EAX, R_DBR );
1.1155 + }
1.1156 + break;
1.1157 + default:
1.1158 + UNDEF();
1.1159 + break;
1.1160 + }
1.1161 + break;
1.1162 + case 0xB:
1.1163 + switch( (ir&0xF0) >> 4 ) {
1.1164 + case 0x0:
1.1165 + { /* JSR @Rn */
1.1166 + uint32_t Rn = ((ir>>8)&0xF);
1.1167 + }
1.1168 + break;
1.1169 + case 0x1:
1.1170 + { /* TAS.B @Rn */
1.1171 + uint32_t Rn = ((ir>>8)&0xF);
1.1172 + }
1.1173 + break;
1.1174 + case 0x2:
1.1175 + { /* JMP @Rn */
1.1176 + uint32_t Rn = ((ir>>8)&0xF);
1.1177 + }
1.1178 + break;
1.1179 + default:
1.1180 + UNDEF();
1.1181 + break;
1.1182 + }
1.1183 + break;
1.1184 + case 0xC:
1.1185 + { /* SHAD Rm, Rn */
1.1186 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1187 + /* Annoyingly enough, not directly convertible */
1.1188 + }
1.1189 + break;
1.1190 + case 0xD:
1.1191 + { /* SHLD Rm, Rn */
1.1192 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1193 + }
1.1194 + break;
1.1195 + case 0xE:
1.1196 + switch( (ir&0x80) >> 7 ) {
1.1197 + case 0x0:
1.1198 + switch( (ir&0x70) >> 4 ) {
1.1199 + case 0x0:
1.1200 + { /* LDC Rm, SR */
1.1201 + uint32_t Rm = ((ir>>8)&0xF);
1.1202 + /* We need to be a little careful about SR */
1.1203 + }
1.1204 + break;
1.1205 + case 0x1:
1.1206 + { /* LDC Rm, GBR */
1.1207 + uint32_t Rm = ((ir>>8)&0xF);
1.1208 + load_reg( R_EAX, Rm );
1.1209 + store_spreg( R_EAX, R_GBR );
1.1210 + }
1.1211 + break;
1.1212 + case 0x2:
1.1213 + { /* LDC Rm, VBR */
1.1214 + uint32_t Rm = ((ir>>8)&0xF);
1.1215 + load_reg( R_EAX, Rm );
1.1216 + store_spreg( R_EAX, R_VBR );
1.1217 + }
1.1218 + break;
1.1219 + case 0x3:
1.1220 + { /* LDC Rm, SSR */
1.1221 + uint32_t Rm = ((ir>>8)&0xF);
1.1222 + load_reg( R_EAX, Rm );
1.1223 + store_spreg( R_EAX, R_SSR );
1.1224 + }
1.1225 + break;
1.1226 + case 0x4:
1.1227 + { /* LDC Rm, SPC */
1.1228 + uint32_t Rm = ((ir>>8)&0xF);
1.1229 + load_reg( R_EAX, Rm );
1.1230 + store_spreg( R_EAX, R_SPC );
1.1231 + }
1.1232 + break;
1.1233 + default:
1.1234 + UNDEF();
1.1235 + break;
1.1236 + }
1.1237 + break;
1.1238 + case 0x1:
1.1239 + { /* LDC Rm, Rn_BANK */
1.1240 + uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1.1241 + }
1.1242 + break;
1.1243 + }
1.1244 + break;
1.1245 + case 0xF:
1.1246 + { /* MAC.W @Rm+, @Rn+ */
1.1247 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1248 + }
1.1249 + break;
1.1250 + }
1.1251 + break;
1.1252 + case 0x5:
1.1253 + { /* MOV.L @(disp, Rm), Rn */
1.1254 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1.1255 + }
1.1256 + break;
1.1257 + case 0x6:
1.1258 + switch( ir&0xF ) {
1.1259 + case 0x0:
1.1260 + { /* MOV.B @Rm, Rn */
1.1261 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1262 + load_reg( R_ECX, Rm );
1.1263 + MEM_READ_BYTE( R_ECX, R_EAX );
1.1264 + store_reg( R_ECX, Rn );
1.1265 + }
1.1266 + break;
1.1267 + case 0x1:
1.1268 + { /* MOV.W @Rm, Rn */
1.1269 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1270 + }
1.1271 + break;
1.1272 + case 0x2:
1.1273 + { /* MOV.L @Rm, Rn */
1.1274 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1275 + }
1.1276 + break;
1.1277 + case 0x3:
1.1278 + { /* MOV Rm, Rn */
1.1279 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1280 + load_reg( R_EAX, Rm );
1.1281 + store_reg( R_EAX, Rn );
1.1282 + }
1.1283 + break;
1.1284 + case 0x4:
1.1285 + { /* MOV.B @Rm+, Rn */
1.1286 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1287 + load_reg( R_ECX, Rm );
1.1288 + MOV_r32_r32( R_ECX, R_EAX );
1.1289 + ADD_imm8s_r32( 1, R_EAX );
1.1290 + store_reg( R_EAX, Rm );
1.1291 + MEM_READ_BYTE( R_ECX, R_EAX );
1.1292 + store_reg( R_EAX, Rn );
1.1293 + }
1.1294 + break;
1.1295 + case 0x5:
1.1296 + { /* MOV.W @Rm+, Rn */
1.1297 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1298 + }
1.1299 + break;
1.1300 + case 0x6:
1.1301 + { /* MOV.L @Rm+, Rn */
1.1302 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1303 + }
1.1304 + break;
1.1305 + case 0x7:
1.1306 + { /* NOT Rm, Rn */
1.1307 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1308 + load_reg( R_EAX, Rm );
1.1309 + NOT_r32( R_EAX );
1.1310 + store_reg( R_EAX, Rn );
1.1311 + }
1.1312 + break;
1.1313 + case 0x8:
1.1314 + { /* SWAP.B Rm, Rn */
1.1315 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1316 + load_reg( R_EAX, Rm );
1.1317 + XCHG_r8_r8( R_AL, R_AH );
1.1318 + store_reg( R_EAX, Rn );
1.1319 + }
1.1320 + break;
1.1321 + case 0x9:
1.1322 + { /* SWAP.W Rm, Rn */
1.1323 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1324 + load_reg( R_EAX, Rm );
1.1325 + MOV_r32_r32( R_EAX, R_ECX );
1.1326 + SHL_imm8_r32( 16, R_ECX );
1.1327 + SHR_imm8_r32( 16, R_EAX );
1.1328 + OR_r32_r32( R_EAX, R_ECX );
1.1329 + store_reg( R_ECX, Rn );
1.1330 + }
1.1331 + break;
1.1332 + case 0xA:
1.1333 + { /* NEGC Rm, Rn */
1.1334 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1335 + load_reg( R_EAX, Rm );
1.1336 + XOR_r32_r32( R_ECX, R_ECX );
1.1337 + LDC_t();
1.1338 + SBB_r32_r32( R_EAX, R_ECX );
1.1339 + store_reg( R_ECX, Rn );
1.1340 + SETC_t();
1.1341 + }
1.1342 + break;
1.1343 + case 0xB:
1.1344 + { /* NEG Rm, Rn */
1.1345 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1346 + load_reg( R_EAX, Rm );
1.1347 + NEG_r32( R_EAX );
1.1348 + store_reg( R_EAX, Rn );
1.1349 + }
1.1350 + break;
1.1351 + case 0xC:
1.1352 + { /* EXTU.B Rm, Rn */
1.1353 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1354 + }
1.1355 + break;
1.1356 + case 0xD:
1.1357 + { /* EXTU.W Rm, Rn */
1.1358 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1359 + }
1.1360 + break;
1.1361 + case 0xE:
1.1362 + { /* EXTS.B Rm, Rn */
1.1363 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1364 + load_reg( R_EAX, Rm );
1.1365 + MOVSX_r8_r32( R_EAX, R_EAX );
1.1366 + store_reg( R_EAX, Rn );
1.1367 + }
1.1368 + break;
1.1369 + case 0xF:
1.1370 + { /* EXTS.W Rm, Rn */
1.1371 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1372 + }
1.1373 + break;
1.1374 + }
1.1375 + break;
1.1376 + case 0x7:
1.1377 + { /* ADD #imm, Rn */
1.1378 + uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1.1379 + load_reg( R_EAX, Rn );
1.1380 + ADD_imm8s_r32( imm, R_EAX );
1.1381 + store_reg( R_EAX, Rn );
1.1382 + }
1.1383 + break;
1.1384 + case 0x8:
1.1385 + switch( (ir&0xF00) >> 8 ) {
1.1386 + case 0x0:
1.1387 + { /* MOV.B R0, @(disp, Rn) */
1.1388 + uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1.1389 + load_reg( R_EAX, 0 );
1.1390 + load_reg( R_ECX, Rn );
1.1391 + ADD_imm32_r32( disp, R_ECX );
1.1392 + MEM_WRITE_BYTE( R_ECX, R_EAX );
1.1393 + }
1.1394 + break;
1.1395 + case 0x1:
1.1396 + { /* MOV.W R0, @(disp, Rn) */
1.1397 + uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1.1398 + }
1.1399 + break;
1.1400 + case 0x4:
1.1401 + { /* MOV.B @(disp, Rm), R0 */
1.1402 + uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1.1403 + load_reg( R_ECX, Rm );
1.1404 + ADD_imm32_r32( disp, R_ECX );
1.1405 + MEM_READ_BYTE( R_ECX, R_EAX );
1.1406 + store_reg( R_EAX, 0 );
1.1407 + }
1.1408 + break;
1.1409 + case 0x5:
1.1410 + { /* MOV.W @(disp, Rm), R0 */
1.1411 + uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1.1412 + }
1.1413 + break;
1.1414 + case 0x8:
1.1415 + { /* CMP/EQ #imm, R0 */
1.1416 + int32_t imm = SIGNEXT8(ir&0xFF);
1.1417 + load_reg( R_EAX, 0 );
1.1418 + CMP_imm8s_r32(imm, R_EAX);
1.1419 + SETE_t();
1.1420 + }
1.1421 + break;
1.1422 + case 0x9:
1.1423 + { /* BT disp */
1.1424 + int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1.1425 + /* If true, result PC += 4 + disp. else result PC = pc+2 */
1.1426 + return pc + 2;
1.1427 + }
1.1428 + break;
1.1429 + case 0xB:
1.1430 + { /* BF disp */
1.1431 + int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1.1432 + }
1.1433 + break;
1.1434 + case 0xD:
1.1435 + { /* BT/S disp */
1.1436 + int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1.1437 + return pc + 4;
1.1438 + }
1.1439 + break;
1.1440 + case 0xF:
1.1441 + { /* BF/S disp */
1.1442 + int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1.1443 + }
1.1444 + break;
1.1445 + default:
1.1446 + UNDEF();
1.1447 + break;
1.1448 + }
1.1449 + break;
1.1450 + case 0x9:
1.1451 + { /* MOV.W @(disp, PC), Rn */
1.1452 + uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1.1453 + }
1.1454 + break;
1.1455 + case 0xA:
1.1456 + { /* BRA disp */
1.1457 + int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1.1458 + }
1.1459 + break;
1.1460 + case 0xB:
1.1461 + { /* BSR disp */
1.1462 + int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1.1463 + }
1.1464 + break;
1.1465 + case 0xC:
1.1466 + switch( (ir&0xF00) >> 8 ) {
1.1467 + case 0x0:
1.1468 + { /* MOV.B R0, @(disp, GBR) */
1.1469 + uint32_t disp = (ir&0xFF);
1.1470 + load_reg( R_EAX, 0 );
1.1471 + load_spreg( R_ECX, R_GBR );
1.1472 + ADD_imm32_r32( disp, R_ECX );
1.1473 + MEM_WRITE_BYTE( R_ECX, R_EAX );
1.1474 + }
1.1475 + break;
1.1476 + case 0x1:
1.1477 + { /* MOV.W R0, @(disp, GBR) */
1.1478 + uint32_t disp = (ir&0xFF)<<1;
1.1479 + }
1.1480 + break;
1.1481 + case 0x2:
1.1482 + { /* MOV.L R0, @(disp, GBR) */
1.1483 + uint32_t disp = (ir&0xFF)<<2;
1.1484 + }
1.1485 + break;
1.1486 + case 0x3:
1.1487 + { /* TRAPA #imm */
1.1488 + uint32_t imm = (ir&0xFF);
1.1489 + }
1.1490 + break;
1.1491 + case 0x4:
1.1492 + { /* MOV.B @(disp, GBR), R0 */
1.1493 + uint32_t disp = (ir&0xFF);
1.1494 + load_spreg( R_ECX, R_GBR );
1.1495 + ADD_imm32_r32( disp, R_ECX );
1.1496 + MEM_READ_BYTE( R_ECX, R_EAX );
1.1497 + store_reg( R_EAX, 0 );
1.1498 + }
1.1499 + break;
1.1500 + case 0x5:
1.1501 + { /* MOV.W @(disp, GBR), R0 */
1.1502 + uint32_t disp = (ir&0xFF)<<1;
1.1503 + }
1.1504 + break;
1.1505 + case 0x6:
1.1506 + { /* MOV.L @(disp, GBR), R0 */
1.1507 + uint32_t disp = (ir&0xFF)<<2;
1.1508 + }
1.1509 + break;
1.1510 + case 0x7:
1.1511 + { /* MOVA @(disp, PC), R0 */
1.1512 + uint32_t disp = (ir&0xFF)<<2;
1.1513 + }
1.1514 + break;
1.1515 + case 0x8:
1.1516 + { /* TST #imm, R0 */
1.1517 + uint32_t imm = (ir&0xFF);
1.1518 + }
1.1519 + break;
1.1520 + case 0x9:
1.1521 + { /* AND #imm, R0 */
1.1522 + uint32_t imm = (ir&0xFF);
1.1523 + // Note: x86 AND imm8 sign-extends, SH4 version zero-extends. So
1.1524 + // need to use the imm32 version
1.1525 + load_reg( R_EAX, 0 );
1.1526 + AND_imm32_r32(imm, R_EAX);
1.1527 + store_reg( R_EAX, 0 );
1.1528 + }
1.1529 + break;
1.1530 + case 0xA:
1.1531 + { /* XOR #imm, R0 */
1.1532 + uint32_t imm = (ir&0xFF);
1.1533 + load_reg( R_EAX, 0 );
1.1534 + XOR_imm32_r32( imm, R_EAX );
1.1535 + store_reg( R_EAX, 0 );
1.1536 + }
1.1537 + break;
1.1538 + case 0xB:
1.1539 + { /* OR #imm, R0 */
1.1540 + uint32_t imm = (ir&0xFF);
1.1541 + load_reg( R_EAX, 0 );
1.1542 + OR_imm32_r32(imm, R_EAX);
1.1543 + store_reg( R_EAX, 0 );
1.1544 + }
1.1545 + break;
1.1546 + case 0xC:
1.1547 + { /* TST.B #imm, @(R0, GBR) */
1.1548 + uint32_t imm = (ir&0xFF);
1.1549 + }
1.1550 + break;
1.1551 + case 0xD:
1.1552 + { /* AND.B #imm, @(R0, GBR) */
1.1553 + uint32_t imm = (ir&0xFF);
1.1554 + load_reg( R_EAX, 0 );
1.1555 + load_spreg( R_ECX, R_GBR );
1.1556 + ADD_r32_r32( R_EAX, R_EBX );
1.1557 + MEM_READ_BYTE( R_ECX, R_EAX );
1.1558 + AND_imm32_r32(imm, R_ECX );
1.1559 + MEM_WRITE_BYTE( R_ECX, R_EAX );
1.1560 + }
1.1561 + break;
1.1562 + case 0xE:
1.1563 + { /* XOR.B #imm, @(R0, GBR) */
1.1564 + uint32_t imm = (ir&0xFF);
1.1565 + load_reg( R_EAX, 0 );
1.1566 + load_spreg( R_ECX, R_GBR );
1.1567 + ADD_r32_r32( R_EAX, R_ECX );
1.1568 + MEM_READ_BYTE( R_ECX, R_EAX );
1.1569 + XOR_imm32_r32( imm, R_EAX );
1.1570 + MEM_WRITE_BYTE( R_ECX, R_EAX );
1.1571 + }
1.1572 + break;
1.1573 + case 0xF:
1.1574 + { /* OR.B #imm, @(R0, GBR) */
1.1575 + uint32_t imm = (ir&0xFF);
1.1576 + }
1.1577 + break;
1.1578 + }
1.1579 + break;
1.1580 + case 0xD:
1.1581 + { /* MOV.L @(disp, PC), Rn */
1.1582 + uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
1.1583 + }
1.1584 + break;
1.1585 + case 0xE:
1.1586 + { /* MOV #imm, Rn */
1.1587 + uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1.1588 + load_imm32( R_EAX, imm );
1.1589 + store_reg( R_EAX, Rn );
1.1590 + }
1.1591 + break;
1.1592 + case 0xF:
1.1593 + switch( ir&0xF ) {
1.1594 + case 0x0:
1.1595 + { /* FADD FRm, FRn */
1.1596 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1597 + }
1.1598 + break;
1.1599 + case 0x1:
1.1600 + { /* FSUB FRm, FRn */
1.1601 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1602 + }
1.1603 + break;
1.1604 + case 0x2:
1.1605 + { /* FMUL FRm, FRn */
1.1606 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1607 + }
1.1608 + break;
1.1609 + case 0x3:
1.1610 + { /* FDIV FRm, FRn */
1.1611 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1612 + }
1.1613 + break;
1.1614 + case 0x4:
1.1615 + { /* FCMP/EQ FRm, FRn */
1.1616 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1617 + }
1.1618 + break;
1.1619 + case 0x5:
1.1620 + { /* FCMP/GT FRm, FRn */
1.1621 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1622 + }
1.1623 + break;
1.1624 + case 0x6:
1.1625 + { /* FMOV @(R0, Rm), FRn */
1.1626 + uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1627 + }
1.1628 + break;
1.1629 + case 0x7:
1.1630 + { /* FMOV FRm, @(R0, Rn) */
1.1631 + uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1632 + }
1.1633 + break;
1.1634 + case 0x8:
1.1635 + { /* FMOV @Rm, FRn */
1.1636 + uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1637 + }
1.1638 + break;
1.1639 + case 0x9:
1.1640 + { /* FMOV @Rm+, FRn */
1.1641 + uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1.1642 + }
1.1643 + break;
1.1644 + case 0xA:
1.1645 + { /* FMOV FRm, @Rn */
1.1646 + uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1647 + }
1.1648 + break;
1.1649 + case 0xB:
1.1650 + { /* FMOV FRm, @-Rn */
1.1651 + uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1652 + }
1.1653 + break;
1.1654 + case 0xC:
1.1655 + { /* FMOV FRm, FRn */
1.1656 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1657 + }
1.1658 + break;
1.1659 + case 0xD:
1.1660 + switch( (ir&0xF0) >> 4 ) {
1.1661 + case 0x0:
1.1662 + { /* FSTS FPUL, FRn */
1.1663 + uint32_t FRn = ((ir>>8)&0xF);
1.1664 + }
1.1665 + break;
1.1666 + case 0x1:
1.1667 + { /* FLDS FRm, FPUL */
1.1668 + uint32_t FRm = ((ir>>8)&0xF);
1.1669 + }
1.1670 + break;
1.1671 + case 0x2:
1.1672 + { /* FLOAT FPUL, FRn */
1.1673 + uint32_t FRn = ((ir>>8)&0xF);
1.1674 + }
1.1675 + break;
1.1676 + case 0x3:
1.1677 + { /* FTRC FRm, FPUL */
1.1678 + uint32_t FRm = ((ir>>8)&0xF);
1.1679 + }
1.1680 + break;
1.1681 + case 0x4:
1.1682 + { /* FNEG FRn */
1.1683 + uint32_t FRn = ((ir>>8)&0xF);
1.1684 + }
1.1685 + break;
1.1686 + case 0x5:
1.1687 + { /* FABS FRn */
1.1688 + uint32_t FRn = ((ir>>8)&0xF);
1.1689 + }
1.1690 + break;
1.1691 + case 0x6:
1.1692 + { /* FSQRT FRn */
1.1693 + uint32_t FRn = ((ir>>8)&0xF);
1.1694 + }
1.1695 + break;
1.1696 + case 0x7:
1.1697 + { /* FSRRA FRn */
1.1698 + uint32_t FRn = ((ir>>8)&0xF);
1.1699 + }
1.1700 + break;
1.1701 + case 0x8:
1.1702 + { /* FLDI0 FRn */
1.1703 + uint32_t FRn = ((ir>>8)&0xF);
1.1704 + }
1.1705 + break;
1.1706 + case 0x9:
1.1707 + { /* FLDI1 FRn */
1.1708 + uint32_t FRn = ((ir>>8)&0xF);
1.1709 + }
1.1710 + break;
1.1711 + case 0xA:
1.1712 + { /* FCNVSD FPUL, FRn */
1.1713 + uint32_t FRn = ((ir>>8)&0xF);
1.1714 + }
1.1715 + break;
1.1716 + case 0xB:
1.1717 + { /* FCNVDS FRm, FPUL */
1.1718 + uint32_t FRm = ((ir>>8)&0xF);
1.1719 + }
1.1720 + break;
1.1721 + case 0xE:
1.1722 + { /* FIPR FVm, FVn */
1.1723 + uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
1.1724 + }
1.1725 + break;
1.1726 + case 0xF:
1.1727 + switch( (ir&0x100) >> 8 ) {
1.1728 + case 0x0:
1.1729 + { /* FSCA FPUL, FRn */
1.1730 + uint32_t FRn = ((ir>>9)&0x7)<<1;
1.1731 + }
1.1732 + break;
1.1733 + case 0x1:
1.1734 + switch( (ir&0x200) >> 9 ) {
1.1735 + case 0x0:
1.1736 + { /* FTRV XMTRX, FVn */
1.1737 + uint32_t FVn = ((ir>>10)&0x3);
1.1738 + }
1.1739 + break;
1.1740 + case 0x1:
1.1741 + switch( (ir&0xC00) >> 10 ) {
1.1742 + case 0x0:
1.1743 + { /* FSCHG */
1.1744 + }
1.1745 + break;
1.1746 + case 0x2:
1.1747 + { /* FRCHG */
1.1748 + }
1.1749 + break;
1.1750 + case 0x3:
1.1751 + { /* UNDEF */
1.1752 + }
1.1753 + break;
1.1754 + default:
1.1755 + UNDEF();
1.1756 + break;
1.1757 + }
1.1758 + break;
1.1759 + }
1.1760 + break;
1.1761 + }
1.1762 + break;
1.1763 + default:
1.1764 + UNDEF();
1.1765 + break;
1.1766 + }
1.1767 + break;
1.1768 + case 0xE:
1.1769 + { /* FMAC FR0, FRm, FRn */
1.1770 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1.1771 + }
1.1772 + break;
1.1773 + default:
1.1774 + UNDEF();
1.1775 + break;
1.1776 + }
1.1777 + break;
1.1778 + }
1.1779 +
1.1780 +
1.1781 + return 0;
1.1782 +}
.