filename | src/sh4/sh4core.c |
changeset | 260:c82e26ec0cac |
prev | 246:98054d036a24 |
next | 265:5daf59b7f31b |
author | nkeynes |
date | Wed Jan 03 09:00:17 2007 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Adjust timers when they're read rather than waiting until the next time slice. Also temporarily cut the CPU time by 4. Initialize the FRQCR register to 0x0E0A for convenience |
file | annotate | diff | log | raw |
1.1 --- a/src/sh4/sh4core.c Tue Dec 19 09:54:03 2006 +00001.2 +++ b/src/sh4/sh4core.c Wed Jan 03 09:00:17 2007 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: sh4core.c,v 1.35 2006-12-19 09:54:03 nkeynes Exp $1.6 + * $Id: sh4core.c,v 1.36 2007-01-03 09:00:17 nkeynes Exp $1.7 *1.8 * SH4 emulation core, and parent module for all the SH4 peripheral1.9 * modules.1.10 @@ -90,6 +90,7 @@1.11 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );1.13 /* Peripheral modules */1.14 + CPG_reset();1.15 INTC_reset();1.16 TMU_reset();1.17 SCIF_reset();
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