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lxdream.org :: lxdream/src/sh4/timer.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/timer.c
changeset 260:c82e26ec0cac
prev115:699aa8916803
next264:e3b8a3ab32b8
author nkeynes
date Wed Jan 03 09:00:17 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Adjust timers when they're read rather than waiting until the next time
slice. Also temporarily cut the CPU time by 4.
Initialize the FRQCR register to 0x0E0A for convenience
file annotate diff log raw
1.1 --- a/src/sh4/timer.c Fri Mar 17 12:13:12 2006 +0000
1.2 +++ b/src/sh4/timer.c Wed Jan 03 09:00:17 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: timer.c,v 1.4 2006-03-17 12:13:12 nkeynes Exp $
1.6 + * $Id: timer.c,v 1.5 2007-01-03 09:00:17 nkeynes Exp $
1.7 *
1.8 * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
1.9 * keep things simple (they intertwine a bit).
1.10 @@ -53,7 +53,7 @@
1.11 case FRQCR: /* Frequency control */
1.12 div = ifc_divider[(val >> 6) & 0x07];
1.13 sh4_cpu_freq = sh4_input_freq / div;
1.14 - sh4_cpu_period = 1000 * div / sh4_input_freq;
1.15 + sh4_cpu_period = 4000 * div / sh4_input_freq;
1.16 div = ifc_divider[(val >> 3) & 0x07];
1.17 sh4_bus_freq = sh4_input_freq / div;
1.18 sh4_bus_period = 1000 * div / sh4_input_freq;
1.19 @@ -71,6 +71,17 @@
1.20 MMIO_WRITE( CPG, reg, val );
1.21 }
1.22
1.23 +/**
1.24 + * We don't really know what the default reset value is as it's determined
1.25 + * by the mode select pins. This is the standard value that the BIOS sets,
1.26 + * however, so it works for now.
1.27 + */
1.28 +void CPG_reset( )
1.29 +{
1.30 + mmio_region_CPG_write( FRQCR, 0x0E0A );
1.31 +}
1.32 +
1.33 +
1.34 /********************************** RTC *************************************/
1.35
1.36 uint32_t rtc_output_period;
1.37 @@ -87,6 +98,9 @@
1.38
1.39 /********************************** TMU *************************************/
1.40
1.41 +uint32_t TMU_count( int timer, uint32_t nanosecs );
1.42 +
1.43 +
1.44 #define TCR_ICPF 0x0200
1.45 #define TCR_UNF 0x0100
1.46 #define TCR_UNIE 0x0020
1.47 @@ -103,6 +117,20 @@
1.48
1.49 int32_t mmio_region_TMU_read( uint32_t reg )
1.50 {
1.51 + switch( reg ) {
1.52 + case TCNT0:
1.53 + TMU_count( 0, sh4r.slice_cycle );
1.54 + TMU_timers[0].timer_run = sh4r.slice_cycle;
1.55 + break;
1.56 + case TCNT1:
1.57 + TMU_count( 1, sh4r.slice_cycle );
1.58 + TMU_timers[1].timer_run = sh4r.slice_cycle;
1.59 + break;
1.60 + case TCNT2:
1.61 + TMU_count( 2, sh4r.slice_cycle );
1.62 + TMU_timers[2].timer_run = sh4r.slice_cycle;
1.63 + break;
1.64 + }
1.65 return MMIO_READ( TMU, reg );
1.66 }
1.67
1.68 @@ -159,7 +187,7 @@
1.69
1.70 void TMU_start( int timer )
1.71 {
1.72 - TMU_timers[timer].timer_run = 0;
1.73 + TMU_timers[timer].timer_run = sh4r.slice_cycle;
1.74 TMU_timers[timer].timer_remainder = 0;
1.75 }
1.76
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