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lxdream.org :: lxdream/src/sh4/sh4mmio.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.c
changeset 10:c898b37506e0
prev1:eea311cfd33e
next19:9da7a8e38f9d
author nkeynes
date Sun Dec 11 05:15:36 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Add CPU disasembly options to mode dropdown
Split sh4/mem.c into core mem.c and sh4/mem.c
Start adding copyright comments to file headers
file annotate diff log raw
1.1 --- a/src/sh4/sh4mmio.c Sat Mar 13 00:03:32 2004 +0000
1.2 +++ b/src/sh4/sh4mmio.c Sun Dec 11 05:15:36 2005 +0000
1.3 @@ -9,11 +9,16 @@
1.4
1.5 MMIO_REGION_READ_STUBFN( MMU )
1.6
1.7 +#define OCRAM_START (0x1C000000>>PAGE_BITS)
1.8 +#define OCRAM_END (0x20000000>>PAGE_BITS)
1.9 +
1.10 +static char *cache = NULL;
1.11 +
1.12 void mmio_region_MMU_write( uint32_t reg, uint32_t val )
1.13 {
1.14 switch(reg) {
1.15 case CCR:
1.16 - mem_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
1.17 + mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
1.18 INFO( "Cache mode set to %08X", val );
1.19 break;
1.20 default:
1.21 @@ -23,6 +28,31 @@
1.22 }
1.23
1.24
1.25 +void mmu_init()
1.26 +{
1.27 + cache = mem_alloc_pages(2);
1.28 +}
1.29 +
1.30 +void mmu_set_cache_mode( int mode )
1.31 +{
1.32 + uint32_t i;
1.33 + switch( mode ) {
1.34 + case MEM_OC_INDEX0: /* OIX=0 */
1.35 + for( i=OCRAM_START; i<OCRAM_END; i++ )
1.36 + page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
1.37 + break;
1.38 + case MEM_OC_INDEX1: /* OIX=1 */
1.39 + for( i=OCRAM_START; i<OCRAM_END; i++ )
1.40 + page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
1.41 + break;
1.42 + default: /* disabled */
1.43 + for( i=OCRAM_START; i<OCRAM_END; i++ )
1.44 + page_map[i] = NULL;
1.45 + break;
1.46 + }
1.47 +}
1.48 +
1.49 +
1.50 /********************************* BSC *************************************/
1.51
1.52 uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
.