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lxdream.org :: lxdream/src/sh4/sh4mmio.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.h
changeset 10:c898b37506e0
prev1:eea311cfd33e
next19:9da7a8e38f9d
author nkeynes
date Sun Dec 11 05:15:36 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Add CPU disasembly options to mode dropdown
Split sh4/mem.c into core mem.c and sh4/mem.c
Start adding copyright comments to file headers
file annotate diff log raw
1.1 --- a/src/sh4/sh4mmio.h Sat Mar 13 00:03:32 2004 +0000
1.2 +++ b/src/sh4/sh4mmio.h Sun Dec 11 05:15:36 2005 +0000
1.3 @@ -150,4 +150,37 @@
1.4 MMIO_REGION( SCIF )
1.5 MMIO_REGION_LIST_END
1.6
1.7 +/* mmucr register bits */
1.8 +#define MMUCR_AT 0x00000001 /* Address Translation enabled */
1.9 +#define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */
1.10 +#define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
1.11 +#define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
1.12 +#define MMUCR_URC 0x0000FC00 /* UTLB access counter */
1.13 +#define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */
1.14 +#define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
1.15 +#define MMUCR_MASK 0xFCFCFF05
1.16 +#define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
1.17 +
1.18 +#define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
1.19 +
1.20 +/* ccr register bits */
1.21 +#define CCR_IIX 0x00008000 /* IC index enable */
1.22 +#define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */
1.23 +#define CCR_ICE 0x00000100 /* IC enable */
1.24 +#define CCR_OIX 0x00000080 /* OC index enable */
1.25 +#define CCR_ORA 0x00000020 /* OC RAM enable */
1.26 +#define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */
1.27 +#define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */
1.28 +#define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */
1.29 +#define CCR_OCE 0x00000001 /* OC enable */
1.30 +#define CCR_MASK 0x000089AF
1.31 +#define CCR_RMASK 0x000081A7 /* Read mask */
1.32 +
1.33 +#define MEM_OC_DISABLED 0
1.34 +#define MEM_OC_INDEX0 CCR_ORA
1.35 +#define MEM_OC_INDEX1 CCR_ORA|CCR_OIX
1.36 +
1.37 +void mmu_init(void);
1.38 +void mmu_set_cache_mode( int );
1.39 +
1.40 #endif
.