1.1 --- a/src/sh4/mmu.c	Sun Aug 24 02:43:28 2008 +0000
     1.2 +++ b/src/sh4/mmu.c	Tue Oct 14 07:02:42 2008 +0000
     1.3 @@ -192,10 +192,12 @@
     1.4      	val &= 0x0000001C;
     1.5      	break;
     1.6      case PMCR1:
     1.7 +        PMM_write_control(0, val);
     1.8 +        val &= 0x0000C13F;
     1.9 +        break;
    1.10      case PMCR2:
    1.11 -        if( val != 0 ) {
    1.12 -            WARN( "Performance counters not implemented" );
    1.13 -        }
    1.14 +        PMM_write_control(1, val);
    1.15 +        val &= 0x0000C13F;
    1.16          break;
    1.17      default:
    1.18          break;
    1.19 @@ -964,19 +966,3 @@
    1.20      return TRUE;
    1.21  }
    1.22  
    1.23 -/********************************* PMM *************************************/
    1.24 -
    1.25 -/**
    1.26 - * Side note - this is here (rather than in sh4mmio.c) as the control registers
    1.27 - * are part of the MMU block, and it seems simplest to keep it all together.
    1.28 - */
    1.29 -
    1.30 -int32_t mmio_region_PMM_read( uint32_t reg )
    1.31 -{
    1.32 -    return MMIO_READ( PMM, reg );
    1.33 -}
    1.34 -
    1.35 -void mmio_region_PMM_write( uint32_t reg, uint32_t val )
    1.36 -{
    1.37 -    /* Read-only */
    1.38 -}