1.1 --- a/src/sh4/sh4.c	Tue Jul 21 20:21:52 2009 +1000
     1.2 +++ b/src/sh4/sh4.c	Mon Dec 21 08:23:54 2009 +1000
     1.3 @@ -42,7 +42,6 @@
     1.4  #endif
     1.5  
     1.6  void sh4_init( void );
     1.7 -void sh4_xlat_init( void );
     1.8  void sh4_poweron_reset( void );
     1.9  void sh4_start( void );
    1.10  void sh4_stop( void );
    1.11 @@ -54,54 +53,53 @@
    1.12  size_t sh4_debug_write_vma( uint32_t addr, unsigned char *buf, size_t length );
    1.13  
    1.14  uint32_t sh4_run_slice( uint32_t );
    1.15 -uint32_t sh4_xlat_run_slice( uint32_t );
    1.16  
    1.17  /* Note: this must match GDB's ordering */
    1.18  const struct reg_desc_struct sh4_reg_map[] = 
    1.19 -  { {"R0", REG_INT, &sh4r.r[0]}, {"R1", REG_INT, &sh4r.r[1]},
    1.20 -    {"R2", REG_INT, &sh4r.r[2]}, {"R3", REG_INT, &sh4r.r[3]},
    1.21 -    {"R4", REG_INT, &sh4r.r[4]}, {"R5", REG_INT, &sh4r.r[5]},
    1.22 -    {"R6", REG_INT, &sh4r.r[6]}, {"R7", REG_INT, &sh4r.r[7]},
    1.23 -    {"R8", REG_INT, &sh4r.r[8]}, {"R9", REG_INT, &sh4r.r[9]},
    1.24 -    {"R10",REG_INT, &sh4r.r[10]}, {"R11",REG_INT, &sh4r.r[11]},
    1.25 -    {"R12",REG_INT, &sh4r.r[12]}, {"R13",REG_INT, &sh4r.r[13]},
    1.26 -    {"R14",REG_INT, &sh4r.r[14]}, {"R15",REG_INT, &sh4r.r[15]},
    1.27 -    {"PC", REG_INT, &sh4r.pc}, {"PR", REG_INT, &sh4r.pr},
    1.28 -    {"GBR", REG_INT, &sh4r.gbr}, {"VBR",REG_INT, &sh4r.vbr}, 
    1.29 -    {"MACH",REG_INT, ((uint32_t *)&sh4r.mac)+1}, {"MACL",REG_INT, &sh4r.mac},
    1.30 -    {"SR", REG_INT, &sh4r.sr},
    1.31 -    {"FPUL", REG_INT, &sh4r.fpul.i}, {"FPSCR", REG_INT, &sh4r.fpscr},
    1.32 +  { {"R0", REG_TYPE_INT, &sh4r.r[0]}, {"R1", REG_TYPE_INT, &sh4r.r[1]},
    1.33 +    {"R2", REG_TYPE_INT, &sh4r.r[2]}, {"R3", REG_TYPE_INT, &sh4r.r[3]},
    1.34 +    {"R4", REG_TYPE_INT, &sh4r.r[4]}, {"R5", REG_TYPE_INT, &sh4r.r[5]},
    1.35 +    {"R6", REG_TYPE_INT, &sh4r.r[6]}, {"R7", REG_TYPE_INT, &sh4r.r[7]},
    1.36 +    {"R8", REG_TYPE_INT, &sh4r.r[8]}, {"R9", REG_TYPE_INT, &sh4r.r[9]},
    1.37 +    {"R10",REG_TYPE_INT, &sh4r.r[10]}, {"R11",REG_TYPE_INT, &sh4r.r[11]},
    1.38 +    {"R12",REG_TYPE_INT, &sh4r.r[12]}, {"R13",REG_TYPE_INT, &sh4r.r[13]},
    1.39 +    {"R14",REG_TYPE_INT, &sh4r.r[14]}, {"R15",REG_TYPE_INT, &sh4r.r[15]},
    1.40 +    {"PC", REG_TYPE_INT, &sh4r.pc}, {"PR", REG_TYPE_INT, &sh4r.pr},
    1.41 +    {"GBR", REG_TYPE_INT, &sh4r.gbr}, {"VBR",REG_TYPE_INT, &sh4r.vbr}, 
    1.42 +    {"MACH",REG_TYPE_INT, ((uint32_t *)&sh4r.mac)+1}, {"MACL",REG_TYPE_INT, &sh4r.mac},
    1.43 +    {"SR", REG_TYPE_INT, &sh4r.sr},
    1.44 +    {"FPUL", REG_TYPE_INT, &sh4r.fpul.i}, {"FPSCR", REG_TYPE_INT, &sh4r.fpscr},
    1.45      
    1.46 -    {"FR0", REG_FLOAT, &sh4r.fr[0][1] },{"FR1", REG_FLOAT, &sh4r.fr[0][0]},
    1.47 -    {"FR2", REG_FLOAT, &sh4r.fr[0][3] },{"FR3", REG_FLOAT, &sh4r.fr[0][2]},
    1.48 -    {"FR4", REG_FLOAT, &sh4r.fr[0][5] },{"FR5", REG_FLOAT, &sh4r.fr[0][4]},
    1.49 -    {"FR6", REG_FLOAT, &sh4r.fr[0][7] },{"FR7", REG_FLOAT, &sh4r.fr[0][6]},
    1.50 -    {"FR8", REG_FLOAT, &sh4r.fr[0][9] },{"FR9", REG_FLOAT, &sh4r.fr[0][8]},
    1.51 -    {"FR10", REG_FLOAT, &sh4r.fr[0][11] },{"FR11", REG_FLOAT, &sh4r.fr[0][10]},
    1.52 -    {"FR12", REG_FLOAT, &sh4r.fr[0][13] },{"FR13", REG_FLOAT, &sh4r.fr[0][12]},
    1.53 -    {"FR14", REG_FLOAT, &sh4r.fr[0][15] },{"FR15", REG_FLOAT, &sh4r.fr[0][14]},
    1.54 +    {"FR0", REG_TYPE_FLOAT, &sh4r.fr[0][1] },{"FR1", REG_TYPE_FLOAT, &sh4r.fr[0][0]},
    1.55 +    {"FR2", REG_TYPE_FLOAT, &sh4r.fr[0][3] },{"FR3", REG_TYPE_FLOAT, &sh4r.fr[0][2]},
    1.56 +    {"FR4", REG_TYPE_FLOAT, &sh4r.fr[0][5] },{"FR5", REG_TYPE_FLOAT, &sh4r.fr[0][4]},
    1.57 +    {"FR6", REG_TYPE_FLOAT, &sh4r.fr[0][7] },{"FR7", REG_TYPE_FLOAT, &sh4r.fr[0][6]},
    1.58 +    {"FR8", REG_TYPE_FLOAT, &sh4r.fr[0][9] },{"FR9", REG_TYPE_FLOAT, &sh4r.fr[0][8]},
    1.59 +    {"FR10", REG_TYPE_FLOAT, &sh4r.fr[0][11] },{"FR11", REG_TYPE_FLOAT, &sh4r.fr[0][10]},
    1.60 +    {"FR12", REG_TYPE_FLOAT, &sh4r.fr[0][13] },{"FR13", REG_TYPE_FLOAT, &sh4r.fr[0][12]},
    1.61 +    {"FR14", REG_TYPE_FLOAT, &sh4r.fr[0][15] },{"FR15", REG_TYPE_FLOAT, &sh4r.fr[0][14]},
    1.62  
    1.63 -    {"SSR",REG_INT, &sh4r.ssr}, {"SPC", REG_INT, &sh4r.spc},
    1.64 +    {"SSR",REG_TYPE_INT, &sh4r.ssr}, {"SPC", REG_TYPE_INT, &sh4r.spc},
    1.65      
    1.66 -    {"R0B0", REG_INT, NULL}, {"R1B0", REG_INT, NULL},
    1.67 -    {"R2B0", REG_INT, NULL}, {"R3B0", REG_INT, NULL},
    1.68 -    {"R4B0", REG_INT, NULL}, {"R5B0", REG_INT, NULL},
    1.69 -    {"R6B0", REG_INT, NULL}, {"R7B0", REG_INT, NULL},
    1.70 -    {"R0B1", REG_INT, NULL}, {"R1B1", REG_INT, NULL},
    1.71 -    {"R2B1", REG_INT, NULL}, {"R3B1", REG_INT, NULL},
    1.72 -    {"R4B1", REG_INT, NULL}, {"R5B1", REG_INT, NULL},
    1.73 -    {"R6B1", REG_INT, NULL}, {"R7B1", REG_INT, NULL},
    1.74 +    {"R0B0", REG_TYPE_INT, NULL}, {"R1B0", REG_TYPE_INT, NULL},
    1.75 +    {"R2B0", REG_TYPE_INT, NULL}, {"R3B0", REG_TYPE_INT, NULL},
    1.76 +    {"R4B0", REG_TYPE_INT, NULL}, {"R5B0", REG_TYPE_INT, NULL},
    1.77 +    {"R6B0", REG_TYPE_INT, NULL}, {"R7B0", REG_TYPE_INT, NULL},
    1.78 +    {"R0B1", REG_TYPE_INT, NULL}, {"R1B1", REG_TYPE_INT, NULL},
    1.79 +    {"R2B1", REG_TYPE_INT, NULL}, {"R3B1", REG_TYPE_INT, NULL},
    1.80 +    {"R4B1", REG_TYPE_INT, NULL}, {"R5B1", REG_TYPE_INT, NULL},
    1.81 +    {"R6B1", REG_TYPE_INT, NULL}, {"R7B1", REG_TYPE_INT, NULL},
    1.82      
    1.83 -    {"SGR",REG_INT, &sh4r.sgr}, {"DBR", REG_INT, &sh4r.dbr},
    1.84 +    {"SGR",REG_TYPE_INT, &sh4r.sgr}, {"DBR", REG_TYPE_INT, &sh4r.dbr},
    1.85  
    1.86 -    {"XF0", REG_FLOAT, &sh4r.fr[1][1] },{"XF1", REG_FLOAT, &sh4r.fr[1][0]},
    1.87 -    {"XF2", REG_FLOAT, &sh4r.fr[1][3] },{"XF3", REG_FLOAT, &sh4r.fr[1][2]},
    1.88 -    {"XF4", REG_FLOAT, &sh4r.fr[1][5] },{"XF5", REG_FLOAT, &sh4r.fr[1][4]},
    1.89 -    {"XF6", REG_FLOAT, &sh4r.fr[1][7] },{"XF7", REG_FLOAT, &sh4r.fr[1][6]},
    1.90 -    {"XF8", REG_FLOAT, &sh4r.fr[1][9] },{"XF9", REG_FLOAT, &sh4r.fr[1][8]},
    1.91 -    {"XF10", REG_FLOAT, &sh4r.fr[1][11] },{"XF11", REG_FLOAT, &sh4r.fr[1][10]},
    1.92 -    {"XF12", REG_FLOAT, &sh4r.fr[1][13] },{"XF13", REG_FLOAT, &sh4r.fr[1][12]},
    1.93 -    {"XF14", REG_FLOAT, &sh4r.fr[1][15] },{"XF15", REG_FLOAT, &sh4r.fr[1][14]},
    1.94 +    {"XF0", REG_TYPE_FLOAT, &sh4r.fr[1][1] },{"XF1", REG_TYPE_FLOAT, &sh4r.fr[1][0]},
    1.95 +    {"XF2", REG_TYPE_FLOAT, &sh4r.fr[1][3] },{"XF3", REG_TYPE_FLOAT, &sh4r.fr[1][2]},
    1.96 +    {"XF4", REG_TYPE_FLOAT, &sh4r.fr[1][5] },{"XF5", REG_TYPE_FLOAT, &sh4r.fr[1][4]},
    1.97 +    {"XF6", REG_TYPE_FLOAT, &sh4r.fr[1][7] },{"XF7", REG_TYPE_FLOAT, &sh4r.fr[1][6]},
    1.98 +    {"XF8", REG_TYPE_FLOAT, &sh4r.fr[1][9] },{"XF9", REG_TYPE_FLOAT, &sh4r.fr[1][8]},
    1.99 +    {"XF10", REG_TYPE_FLOAT, &sh4r.fr[1][11] },{"XF11", REG_TYPE_FLOAT, &sh4r.fr[1][10]},
   1.100 +    {"XF12", REG_TYPE_FLOAT, &sh4r.fr[1][13] },{"XF13", REG_TYPE_FLOAT, &sh4r.fr[1][12]},
   1.101 +    {"XF14", REG_TYPE_FLOAT, &sh4r.fr[1][15] },{"XF15", REG_TYPE_FLOAT, &sh4r.fr[1][14]},
   1.102      
   1.103      {NULL, 0, NULL} };
   1.104  
   1.105 @@ -390,6 +388,19 @@
   1.106      sh4r.new_pc = pc+2;
   1.107  }
   1.108  
   1.109 +/**
   1.110 + * Dump all SH4 core information for crash-dump purposes
   1.111 + */
   1.112 +void sh4_crashdump()
   1.113 +{
   1.114 +    cpu_print_registers( stderr, &sh4_cpu_desc );
   1.115 +#ifdef SH4_TRANSLATOR
   1.116 +    if( sh4_use_translator ) {
   1.117 +        sh4_translate_crashdump();
   1.118 +    } /* Nothing really to print for emu core */
   1.119 +#endif
   1.120 +}
   1.121 +
   1.122  
   1.123  /******************************* Support methods ***************************/
   1.124