1.1 --- a/src/pvr2/pvr2.h Sun Jul 20 11:36:48 2008 +0000
1.2 +++ b/src/pvr2/pvr2.h Sun Aug 24 02:57:15 2008 +0000
1.4 #define BS_PALM 0x00000080 /* ? */
1.5 #define BS_PALN 0x000000C0 /* ? */
1.7 +#define SCALER_HSCALE 0x00010000
1.9 #define PVR2_RAM_BASE 0x05000000
1.10 #define PVR2_RAM_BASE_INT 0x04000000
1.11 #define PVR2_RAM_SIZE (8 * 1024 * 1024)
1.13 /****************************** Frame Buffer *****************************/
1.16 - * Write a block of data to an address in the DMA range (0x10000000 -
1.17 + * Write a block of data to an address in the DMA range (0x10000000 -
1.18 * 0x13FFFFFF), ie TA, YUV, or texture ram.
1.20 void pvr2_dma_write( sh4addr_t dest, unsigned char *src, uint32_t length );
1.24 * Read a twiddled image from interleaved memory address space (aka 64-bit address
1.25 - * space), writing the image to the destination buffer in detwiddled format.
1.26 + * space), writing the image to the destination buffer in detwiddled format.
1.27 * Width and height must be powers of 2
1.28 * This version reads 4-bit pixels.
1.33 * Read a twiddled image from interleaved memory address space (aka 64-bit address
1.34 - * space), writing the image to the destination buffer in detwiddled format.
1.35 + * space), writing the image to the destination buffer in detwiddled format.
1.36 * Width and height must be powers of 2
1.37 * This version reads 8-bit pixels.
1.39 @@ -170,21 +172,21 @@
1.42 * Read a twiddled image from interleaved memory address space (aka 64-bit address
1.43 - * space), writing the image to the destination buffer in detwiddled format.
1.44 + * space), writing the image to the destination buffer in detwiddled format.
1.45 * Width and height must be powers of 2, and src must be 16-bit aligned.
1.46 * This version reads 16-bit pixels.
1.48 void pvr2_vram64_read_twiddled_16( unsigned char *dest, sh4addr_t src, uint32_t width, uint32_t height );
1.51 - * Read an image from the interleaved memory address space (aka 64-bit address space)
1.52 + * Read an image from the interleaved memory address space (aka 64-bit address space)
1.53 * where the source and destination line sizes may differ. Note that both byte
1.54 * counts must be a multiple of 4, and the src address must be 32-bit aligned.
1.56 void pvr2_vram64_read_stride( unsigned char *dest, uint32_t dest_line_bytes, sh4addr_t srcaddr,
1.57 uint32_t src_line_bytes, uint32_t line_count );
1.59 - * Dump a portion of vram to a stream from the interleaved memory address
1.60 + * Dump a portion of vram to a stream from the interleaved memory address
1.63 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f );
1.66 * @param buffer A render buffer indicating the address to store to, and the
1.67 * format the data needs to be in.
1.68 - * @param backBuffer TRUE to flush the back buffer, FALSE for
1.69 + * @param backBuffer TRUE to flush the back buffer, FALSE for
1.72 void pvr2_render_buffer_copy_to_sh4( render_buffer_t buffer );
1.75 * Find the first polygon or sprite context in the supplied buffer of TA
1.77 - * @return A pointer to the context, or NULL if it cannot be found
1.78 + * @return A pointer to the context, or NULL if it cannot be found
1.80 uint32_t *pvr2_ta_find_polygon_context( uint32_t *buf, uint32_t length );
1.83 * Flush all textures and delete. The cache will be non-functional until
1.84 * the next call to texcache_init(). This would typically be done if
1.85 * switching GL targets.
1.88 void texcache_shutdown( void );
1.92 * multiple interpretations). We use the texture address as the primary
1.93 * index, but allow for multiple instances at each address. The texture
1.94 * will be bound to the GL_TEXTURE_2D target before being returned.
1.97 * If the texture has already been bound, return the ID to which it was
1.98 * bound. Otherwise obtain an unused texture ID and set it up appropriately.
lxdream 0.9.1