1.1 --- a/src/sh4/cache.c	Sat Jan 03 03:30:26 2009 +0000
     1.2 +++ b/src/sh4/cache.c	Tue Jan 06 01:58:08 2009 +0000
     1.3 @@ -24,6 +24,7 @@
     1.4  #include "sh4/sh4core.h"
     1.5  #include "sh4/sh4mmio.h"
     1.6  #include "sh4/xltcache.h"
     1.7 +#include "sh4/mmu.h"
     1.8  
     1.9  #define OCRAM_START (0x7C000000>>LXDREAM_PAGE_BITS)
    1.10  #define OCRAM_MID   (0x7E000000>>LXDREAM_PAGE_BITS)
    1.11 @@ -79,7 +80,6 @@
    1.12      return 0;
    1.13  }
    1.14  
    1.15 -
    1.16  /************************* OCRAM memory address space ************************/
    1.17  
    1.18  #define OCRAMPAGE0 (&ccn_ocache_data[4096])  /* Lines 128-255 */
    1.19 @@ -122,7 +122,8 @@
    1.20          ocram_page0_read_long, ocram_page0_write_long,
    1.21          ocram_page0_read_word, ocram_page0_write_word,
    1.22          ocram_page0_read_byte, ocram_page0_write_byte,
    1.23 -        ocram_page0_read_burst, ocram_page0_write_burst };
    1.24 +        ocram_page0_read_burst, ocram_page0_write_burst,
    1.25 +        unmapped_prefetch };
    1.26  
    1.27  static int32_t FASTCALL ocram_page1_read_long( sh4addr_t addr )
    1.28  {
    1.29 @@ -161,7 +162,8 @@
    1.30          ocram_page1_read_long, ocram_page1_write_long,
    1.31          ocram_page1_read_word, ocram_page1_write_word,
    1.32          ocram_page1_read_byte, ocram_page1_write_byte,
    1.33 -        ocram_page1_read_burst, ocram_page1_write_burst };
    1.34 +        ocram_page1_read_burst, ocram_page1_write_burst,
    1.35 +        unmapped_prefetch };
    1.36  
    1.37  /************************** Cache direct access ******************************/
    1.38  
    1.39 @@ -187,7 +189,8 @@
    1.40          ccn_icache_addr_read, ccn_icache_addr_write,
    1.41          unmapped_read_long, unmapped_write_long,
    1.42          unmapped_read_long, unmapped_write_long,
    1.43 -        unmapped_read_burst, unmapped_write_burst };
    1.44 +        unmapped_read_burst, unmapped_write_burst,
    1.45 +        unmapped_prefetch };
    1.46  
    1.47  
    1.48  static int32_t ccn_icache_data_read( sh4addr_t addr )
    1.49 @@ -206,7 +209,8 @@
    1.50          ccn_icache_data_read, ccn_icache_data_write,
    1.51          unmapped_read_long, unmapped_write_long,
    1.52          unmapped_read_long, unmapped_write_long,
    1.53 -        unmapped_read_burst, unmapped_write_burst };
    1.54 +        unmapped_read_burst, unmapped_write_burst,
    1.55 +        unmapped_prefetch };
    1.56  
    1.57  
    1.58  static int32_t ccn_ocache_addr_read( sh4addr_t addr )
    1.59 @@ -235,7 +239,8 @@
    1.60          ccn_ocache_addr_read, ccn_ocache_addr_write,
    1.61          unmapped_read_long, unmapped_write_long,
    1.62          unmapped_read_long, unmapped_write_long,
    1.63 -        unmapped_read_burst, unmapped_write_burst };
    1.64 +        unmapped_read_burst, unmapped_write_burst,
    1.65 +        unmapped_prefetch };
    1.66  
    1.67  
    1.68  static int32_t ccn_ocache_data_read( sh4addr_t addr )
    1.69 @@ -254,7 +259,8 @@
    1.70          ccn_ocache_data_read, ccn_ocache_data_write,
    1.71          unmapped_read_long, unmapped_write_long,
    1.72          unmapped_read_long, unmapped_write_long,
    1.73 -        unmapped_read_burst, unmapped_write_burst };
    1.74 +        unmapped_read_burst, unmapped_write_burst,
    1.75 +        unmapped_prefetch };
    1.76  
    1.77  
    1.78  /****************** Cache control *********************/
    1.79 @@ -297,19 +303,58 @@
    1.80      }
    1.81  }
    1.82  
    1.83 +/**
    1.84 + * Prefetch for non-storequeue regions
    1.85 + */
    1.86 +void FASTCALL ccn_prefetch( sh4addr_t addr )
    1.87 +{
    1.88 +    
    1.89 +}
    1.90  
    1.91 -/***** Store-queue (considered part of the cache by the SH7750 manual) ******/
    1.92 -static void FASTCALL p4_storequeue_write_long( sh4addr_t addr, uint32_t val )
    1.93 +/**
    1.94 + * Prefetch for non-cached regions. Oddly enough, this does nothing whatsoever.
    1.95 + */
    1.96 +void FASTCALL ccn_uncached_prefetch( sh4addr_t addr )
    1.97 +{
    1.98 +    
    1.99 +}
   1.100 +/********************************* Store-queue *******************************/
   1.101 +/*
   1.102 + * The storequeue is strictly speaking part of the cache, but most of 
   1.103 + * the complexity is actually around its addressing (ie in the MMU). The
   1.104 + * methods here can assume we've already passed SQMD protection and the TLB
   1.105 + * lookups (where appropriate).
   1.106 + */  
   1.107 +void FASTCALL ccn_storequeue_write_long( sh4addr_t addr, uint32_t val )
   1.108  {
   1.109      sh4r.store_queue[(addr>>2)&0xF] = val;
   1.110  }
   1.111 -static int32_t FASTCALL p4_storequeue_read_long( sh4addr_t addr )
   1.112 +int32_t FASTCALL ccn_storequeue_read_long( sh4addr_t addr )
   1.113  {
   1.114      return sh4r.store_queue[(addr>>2)&0xF];
   1.115  }
   1.116  
   1.117 -struct mem_region_fn p4_region_storequeue = { 
   1.118 -        p4_storequeue_read_long, p4_storequeue_write_long,
   1.119 -        p4_storequeue_read_long, p4_storequeue_write_long,
   1.120 -        p4_storequeue_read_long, p4_storequeue_write_long,
   1.121 -        unmapped_read_burst, unmapped_write_burst }; // No burst access.
   1.122 +/**
   1.123 + * Variant used when tlb is disabled - address will be the original prefetch
   1.124 + * address (ie 0xE0001234). Due to the way the SQ addressing is done, it can't
   1.125 + * be hardcoded on 4K page boundaries, so we manually decode it here.
   1.126 + */
   1.127 +void FASTCALL ccn_storequeue_prefetch( sh4addr_t addr ) 
   1.128 +{
   1.129 +    int queue = (addr&0x20)>>2;
   1.130 +    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
   1.131 +    uint32_t hi = MMIO_READ( MMU, QACR0 + (queue>>1)) << 24;
   1.132 +    sh4addr_t target = (addr&0x03FFFFE0) | hi;
   1.133 +    ext_address_space[target>>12]->write_burst( target, src );
   1.134 +}
   1.135 +
   1.136 +/**
   1.137 + * Variant used when tlb is enabled - address in this case is already
   1.138 + * mapped to the external target address.
   1.139 + */
   1.140 +void FASTCALL ccn_storequeue_prefetch_tlb( sh4addr_t addr )
   1.141 +{
   1.142 +    int queue = (addr&0x20)>>2;
   1.143 +    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
   1.144 +    ext_address_space[addr>>12]->write_burst( (addr & 0x1FFFFFE0), src );
   1.145 +}