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lxdream.org :: lxdream/src/sh4/sh4core.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 946:d41ee7994db7
prev945:787729653236
next948:545c85cc56f1
author nkeynes
date Tue Jan 06 01:58:08 2009 +0000 (11 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Fully integrate SQ with the new address space code - added additional 'prefetch'
memory accessor. TLB is utterly untested, but non-TLB at least still works.
file annotate diff log raw
1.1 --- a/src/sh4/sh4core.in Mon Jan 05 04:19:46 2009 +0000
1.2 +++ b/src/sh4/sh4core.in Tue Jan 06 01:58:08 2009 +0000
1.3 @@ -176,6 +176,7 @@
1.4 #define MEM_WRITE_BYTE( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_byte)((addr), (val), &&except)
1.5 #define MEM_WRITE_WORD( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_word)((addr), (val), &&except)
1.6 #define MEM_WRITE_LONG( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_long)((addr), (val), &&except)
1.7 +#define MEM_PREFETCH( addr ) ((mem_prefetch_exc_fn_t)ADDRSPACE[(addr)>>12]->prefetch)((addr), &&except)
1.8 #else
1.9 #define INIT_EXCEPTIONS(label)
1.10 #define MEM_READ_BYTE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte(addr)
1.11 @@ -184,6 +185,7 @@
1.12 #define MEM_WRITE_BYTE( addr, val ) ADDRSPACE[(addr)>>12]->write_byte(addr, val)
1.13 #define MEM_WRITE_WORD( addr, val ) ADDRSPACE[(addr)>>12]->write_word(addr, val)
1.14 #define MEM_WRITE_LONG( addr, val ) ADDRSPACE[(addr)>>12]->write_long(addr, val)
1.15 +#define MEM_PREFETCH( addr ) ADDRSPACE[(addr)>>12]->prefetch(addr)
1.16 #endif
1.17
1.18
1.19 @@ -354,10 +356,7 @@
1.20 NOP {: /* NOP */ :}
1.21
1.22 PREF @Rn {:
1.23 - tmp = sh4r.r[Rn];
1.24 - if( (tmp & 0xFC000000) == 0xE0000000 ) {
1.25 - sh4_flush_store_queue(tmp);
1.26 - }
1.27 + MEM_PREFETCH(sh4r.r[Rn]);
1.28 :}
1.29 OCBI @Rn {: :}
1.30 OCBP @Rn {: :}
.