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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 946:d41ee7994db7
prev941:c67574ed4355
next1067:d3c00ffccfcd
author nkeynes
date Tue Jan 06 01:58:08 2009 +0000 (13 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Fully integrate SQ with the new address space code - added additional 'prefetch'
memory accessor. TLB is utterly untested, but non-TLB at least still works.
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Sat Jan 03 08:55:15 2009 +0000
1.2 +++ b/src/sh4/sh4x86.in Tue Jan 06 01:58:08 2009 +0000
1.3 @@ -311,6 +311,7 @@
1.4 #define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_byte)
1.5 #define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_word)
1.6 #define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_long)
1.7 +#define MEM_PREFETCH( addr_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, prefetch)
1.8
1.9 #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
1.10
1.11 @@ -2501,18 +2502,7 @@
1.12 PREF @Rn {:
1.13 COUNT_INST(I_PREF);
1.14 load_reg( R_EAX, Rn );
1.15 - MOV_r32_r32( R_EAX, R_ECX );
1.16 - AND_imm32_r32( 0xFC000000, R_ECX );
1.17 - CMP_imm32_r32( 0xE0000000, R_ECX );
1.18 - JNE_rel8(end);
1.19 - if( sh4_x86.tlb_on ) {
1.20 - call_func1( sh4_flush_store_queue_mmu, R_EAX );
1.21 - TEST_r32_r32( R_EAX, R_EAX );
1.22 - JE_exc(-1);
1.23 - } else {
1.24 - call_func1( sh4_flush_store_queue, R_EAX );
1.25 - }
1.26 - JMP_TARGET(end);
1.27 + MEM_PREFETCH( R_EAX );
1.28 sh4_x86.tstate = TSTATE_NONE;
1.29 :}
1.30 SLEEP {:
.