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lxdream.org :: lxdream/src/gdrom/ide.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/gdrom/ide.h
changeset 152:d42a4c5cc709
prev149:d88dd2e9a190
next240:9ae4bd697292
author nkeynes
date Tue May 23 13:11:45 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Clean up the buffer and i/o handling
Implement save/load state
file annotate diff log raw
1.1 --- a/src/gdrom/ide.h Sat May 20 06:24:49 2006 +0000
1.2 +++ b/src/gdrom/ide.h Tue May 23 13:11:45 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: ide.h,v 1.7 2006-05-20 06:24:49 nkeynes Exp $
1.6 + * $Id: ide.h,v 1.8 2006-05-23 13:11:45 nkeynes Exp $
1.7 *
1.8 * This file defines the interface and structures of the dreamcast's IDE
1.9 * port. Note that the register definitions are in asic.h, as the registers
1.10 @@ -26,6 +26,7 @@
1.11 #include "dream.h"
1.12
1.13 struct ide_registers {
1.14 + /* IDE interface registers */
1.15 uint8_t status; /* A05F709C + A05F7018 Read-only */
1.16 uint8_t control; /* A05F7018 Write-only 01110 */
1.17 uint8_t error; /* A05F7084 Read-only 10001 */
1.18 @@ -37,33 +38,47 @@
1.19 uint8_t lba2; /* A05F7094 Read/Write 10101 */
1.20 uint8_t device; /* A05F7098 Read/Write 10110 */
1.21 uint8_t command; /* A05F709C Write-only 10111 */
1.22 +
1.23 + /* Internal IDE state */
1.24 uint8_t intrq_pending; /* Flag to indicate if the INTRQ line is active */
1.25 + int state;
1.26
1.27 - /* We don't keep the data register per se, rather the currently pending
1.28 - * data is kept here and read out a byte at a time (in PIO mode) or all at
1.29 - * once (in DMA mode). The IDE routines are responsible for managing this
1.30 - * memory. If dataptr == NULL, there is no data available.
1.31 - */
1.32 - unsigned char *data;
1.33 - uint16_t *readptr, *writeptr;
1.34 - uint16_t gdrom_error; /* Lo-byte = error code, Hi-byte = subcode */
1.35 - int datalen;
1.36 - int blocksize; /* Used to determine the transfer unit size */
1.37 - int blockleft; /* Bytes remaining in the current block */
1.38 + /* Sense response for the last executed packet command */
1.39 + unsigned char gdrom_sense[10];
1.40 +
1.41 +
1.42 + /* offset in the buffer of the next word to read/write, or -1
1.43 + * if inactive.
1.44 + */
1.45 + int data_offset;
1.46 + int data_length;
1.47 +
1.48 + int block_length; /* Used to determine the transfer unit size */
1.49 + int block_left; /* Bytes remaining in the current block */
1.50 };
1.51
1.52 -#define IDE_ST_BUSY 0x80
1.53 -#define IDE_ST_READY 0x40
1.54 -#define IDE_ST_SERV 0x10
1.55 -#define IDE_ST_DATA 0x08
1.56 -#define IDE_ST_ERROR 0x01
1.57 +#define IDE_STATE_IDLE 0
1.58 +#define IDE_STATE_CMD_WRITE 1
1.59 +#define IDE_STATE_PIO_READ 2
1.60 +#define IDE_STATE_PIO_WRITE 3
1.61 +#define IDE_STATE_DMA_READ 4
1.62 +#define IDE_STATE_DMA_WRITE 5
1.63 +#define IDE_STATE_BUSY 6
1.64 +
1.65 +/* Flag bits */
1.66 +#define IDE_STATUS_BSY 0x80 /* Busy */
1.67 +#define IDE_STATUS_DRDY 0x40 /* Device ready */
1.68 +#define IDE_STATUS_DMRD 0x20 /* DMA Request */
1.69 +#define IDE_STATUS_SERV 0x10
1.70 +#define IDE_STATUS_DRQ 0x08
1.71 +#define IDE_STATUS_CHK 0x01 /* Check condition (ie error) */
1.72
1.73 #define IDE_FEAT_DMA 0x01
1.74 #define IDE_FEAT_OVL 0x02
1.75
1.76 -#define IDE_COUNT_CD 0x01
1.77 -#define IDE_COUNT_IO 0x02
1.78 -#define IDE_COUNT_REL 0x04
1.79 +#define IDE_COUNT_CD 0x01 /* Command (1)/Data (0) */
1.80 +#define IDE_COUNT_IO 0x02 /* Input (0)/Output (1) */
1.81 +#define IDE_COUNT_REL 0x04 /* Release device */
1.82
1.83
1.84 #define IDE_CTL_RESET 0x04
1.85 @@ -91,10 +106,13 @@
1.86
1.87
1.88 uint16_t ide_read_data_pio(void);
1.89 +void ide_write_data_pio( uint16_t value );
1.90 +uint32_t ide_read_data_dma( uint32_t addr, uint32_t length );
1.91 uint8_t ide_read_status(void);
1.92 -void ide_write_data_pio( uint16_t value );
1.93 void ide_write_buffer( unsigned char *data, int length );
1.94
1.95 void ide_write_command( uint8_t command );
1.96 void ide_write_control( uint8_t value );
1.97 +
1.98 +void ide_dma_read_req( uint32_t addr, uint32_t length );
1.99 #endif
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