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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 547:d6e00ffc4adc
prev539:75f3e594d4a7
next550:a27e31340147
author nkeynes
date Thu Dec 06 10:37:55 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix stack alignment on x86-64
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Wed Nov 21 11:40:15 2007 +0000
1.2 +++ b/src/sh4/sh4x86.in Thu Dec 06 10:37:55 2007 +0000
1.3 @@ -45,7 +45,7 @@
1.4 gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
1.5 gboolean branch_taken; /* true if we branched unconditionally */
1.6 uint32_t block_start_pc;
1.7 - uint32_t stack_posn; /* Trace stack height for alignment purposes */
1.8 + uint32_t stack_posn; /* Trace stack height for alignment purposes */
1.9 int tstate;
1.10
1.11 /* Allocated memory for the (block-wide) back-patch list */
1.12 @@ -453,9 +453,9 @@
1.13 load_reg( R_EAX, 0 );
1.14 load_spreg( R_ECX, R_GBR );
1.15 ADD_r32_r32( R_EAX, R_ECX );
1.16 - PUSH_r32(R_ECX);
1.17 + PUSH_realigned_r32(R_ECX);
1.18 MEM_READ_BYTE( R_ECX, R_EAX );
1.19 - POP_r32(R_ECX);
1.20 + POP_realigned_r32(R_ECX);
1.21 AND_imm32_r32(imm, R_EAX );
1.22 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.23 sh4_x86.tstate = TSTATE_NONE;
1.24 @@ -625,11 +625,11 @@
1.25 check_ralign32( R_ECX );
1.26 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
1.27 MEM_READ_LONG( R_ECX, R_EAX );
1.28 - PUSH_r32( R_EAX );
1.29 + PUSH_realigned_r32( R_EAX );
1.30 load_reg( R_ECX, Rm );
1.31 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.32 MEM_READ_LONG( R_ECX, R_EAX );
1.33 - POP_r32( R_ECX );
1.34 + POP_realigned_r32( R_ECX );
1.35 IMUL_r32( R_ECX );
1.36 ADD_r32_sh4r( R_EAX, R_MACL );
1.37 ADC_r32_sh4r( R_EDX, R_MACH );
1.38 @@ -649,11 +649,11 @@
1.39 check_ralign16( R_ECX );
1.40 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
1.41 MEM_READ_WORD( R_ECX, R_EAX );
1.42 - PUSH_r32( R_EAX );
1.43 + PUSH_realigned_r32( R_EAX );
1.44 load_reg( R_ECX, Rm );
1.45 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
1.46 MEM_READ_WORD( R_ECX, R_EAX );
1.47 - POP_r32( R_ECX );
1.48 + POP_realigned_r32( R_ECX );
1.49 IMUL_r32( R_ECX );
1.50
1.51 load_spreg( R_ECX, R_S );
1.52 @@ -745,9 +745,9 @@
1.53 load_reg( R_EAX, 0 );
1.54 load_spreg( R_ECX, R_GBR );
1.55 ADD_r32_r32( R_EAX, R_ECX );
1.56 - PUSH_r32(R_ECX);
1.57 + PUSH_realigned_r32(R_ECX);
1.58 MEM_READ_BYTE( R_ECX, R_EAX );
1.59 - POP_r32(R_ECX);
1.60 + POP_realigned_r32(R_ECX);
1.61 OR_imm32_r32(imm, R_EAX );
1.62 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.63 sh4_x86.tstate = TSTATE_NONE;
1.64 @@ -988,9 +988,9 @@
1.65 load_reg( R_EAX, 0 );
1.66 load_spreg( R_ECX, R_GBR );
1.67 ADD_r32_r32( R_EAX, R_ECX );
1.68 - PUSH_r32(R_ECX);
1.69 + PUSH_realigned_r32(R_ECX);
1.70 MEM_READ_BYTE(R_ECX, R_EAX);
1.71 - POP_r32(R_ECX);
1.72 + POP_realigned_r32(R_ECX);
1.73 XOR_imm32_r32( imm, R_EAX );
1.74 MEM_WRITE_BYTE( R_ECX, R_EAX );
1.75 sh4_x86.tstate = TSTATE_NONE;
.