Search
lxdream.org :: lxdream/src/sh4/sh4core.h :: diff
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4core.h
changeset 564:dc7b5ffb0535
prev561:533f6b478071
next569:a1c49e1e8776
author nkeynes
date Tue Jan 01 08:37:26 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Refactor sh4core.h to extract the "public" material into a new sh4.h
file annotate diff log raw
1.1 --- a/src/sh4/sh4core.h Tue Jan 01 05:08:38 2008 +0000
1.2 +++ b/src/sh4/sh4core.h Tue Jan 01 08:37:26 2008 +0000
1.3 @@ -24,96 +24,55 @@
1.4 #include <stdint.h>
1.5 #include <stdio.h>
1.6 #include "mem.h"
1.7 +#include "sh4/sh4.h"
1.8
1.9 #ifdef __cplusplus
1.10 extern "C" {
1.11 -#if 0
1.12 -}
1.13 -#endif
1.14 #endif
1.15
1.16 -
1.17 -/**
1.18 - * SH4 is running normally
1.19 - */
1.20 -#define SH4_STATE_RUNNING 1
1.21 -/**
1.22 - * SH4 is not executing instructions but all peripheral modules are still
1.23 - * running
1.24 - */
1.25 -#define SH4_STATE_SLEEP 2
1.26 -/**
1.27 - * SH4 is not executing instructions, DMAC is halted, but all other peripheral
1.28 - * modules are still running
1.29 - */
1.30 -#define SH4_STATE_DEEP_SLEEP 3
1.31 -/**
1.32 - * SH4 is not executing instructions and all peripheral modules are also
1.33 - * stopped. As close as you can get to powered-off without actually being
1.34 - * off.
1.35 - */
1.36 -#define SH4_STATE_STANDBY 4
1.37 -
1.38 -#define PENDING_IRQ 1
1.39 -#define PENDING_EVENT 2
1.40 -
1.41 -struct sh4_registers {
1.42 - uint32_t r[16];
1.43 - uint32_t sr, pr, pc, fpscr;
1.44 - uint32_t t, m, q, s; /* really boolean - 0 or 1 */
1.45 - int32_t fpul;
1.46 - float *fr_bank;
1.47 - float fr[2][16];
1.48 - uint64_t mac;
1.49 - uint32_t gbr, ssr, spc, sgr, dbr, vbr;
1.50 -
1.51 - uint32_t r_bank[8]; /* hidden banked registers */
1.52 - int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
1.53 -
1.54 - uint32_t new_pc; /* Not a real register, but used to handle delay slots */
1.55 - uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF
1.56 - when no events are pending */
1.57 - uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */
1.58 - int in_delay_slot; /* flag to indicate the current instruction is in
1.59 - * a delay slot (certain rules apply) */
1.60 - uint32_t slice_cycle; /* Current nanosecond within the timeslice */
1.61 - int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
1.62 -};
1.63 -
1.64 -extern struct sh4_registers sh4r;
1.65 +/* Breakpoint data structure */
1.66 extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
1.67 extern int sh4_breakpoint_count;
1.68
1.69 -
1.70 -/* Public functions */
1.71 -void sh4_set_use_xlat( gboolean use );
1.72 +/* SH4 module functions */
1.73 void sh4_init( void );
1.74 void sh4_reset( void );
1.75 void sh4_run( void );
1.76 -void sh4_runto( uint32_t pc, uint32_t count );
1.77 -void sh4_runfor( uint32_t count );
1.78 -int sh4_isrunning( void );
1.79 void sh4_stop( void );
1.80 -void sh4_set_pc( int );
1.81 +
1.82 +/* SH4 peripheral module functions */
1.83 +void CPG_reset( void );
1.84 +void DMAC_reset( void );
1.85 +void DMAC_run_slice( uint32_t );
1.86 +void DMAC_save_state( FILE * );
1.87 +int DMAC_load_state( FILE * );
1.88 +void INTC_reset( void );
1.89 +void INTC_save_state( FILE *f );
1.90 +int INTC_load_state( FILE *f );
1.91 +void MMU_init( void );
1.92 +void MMU_reset( void );
1.93 +void MMU_save_state( FILE *f );
1.94 +int MMU_load_state( FILE *f );
1.95 +void MMU_ldtlb();
1.96 +void SCIF_reset( void );
1.97 +void SCIF_run_slice( uint32_t );
1.98 +void SCIF_save_state( FILE *f );
1.99 +int SCIF_load_state( FILE *f );
1.100 +void SCIF_update_line_speed(void);
1.101 +void TMU_reset( void );
1.102 +void TMU_run_slice( uint32_t );
1.103 +void TMU_save_state( FILE * );
1.104 +int TMU_load_state( FILE * );
1.105 +void TMU_update_clocks( void );
1.106 +
1.107 +/* SH4 instruction support methods */
1.108 void sh4_sleep( void );
1.109 void sh4_fsca( uint32_t angle, float *fr );
1.110 void sh4_ftrv( float *fv, float *xmtrx );
1.111 +uint32_t sh4_read_sr(void);
1.112 +void sh4_write_sr(uint32_t val);
1.113 void signsat48(void);
1.114
1.115 -gboolean sh4_execute_instruction( void );
1.116 -gboolean sh4_raise_exception( int );
1.117 -gboolean sh4_raise_reset( int );
1.118 -gboolean sh4_raise_trap( int );
1.119 -gboolean sh4_raise_slot_exception( int, int );
1.120 -gboolean sh4_raise_tlb_exception( int );
1.121 -void sh4_set_breakpoint( uint32_t pc, int type );
1.122 -gboolean sh4_clear_breakpoint( uint32_t pc, int type );
1.123 -int sh4_get_breakpoint( uint32_t pc );
1.124 -void sh4_accept_interrupt( void );
1.125 -
1.126 -#define BREAK_ONESHOT 1
1.127 -#define BREAK_PERM 2
1.128 -
1.129 /* SH4 Memory */
1.130 uint64_t mmu_vma_to_phys_read( sh4addr_t addr );
1.131 uint64_t mmu_vma_to_phys_write( sh4addr_t addr );
1.132 @@ -131,34 +90,33 @@
1.133 void sh4_flush_store_queue( sh4addr_t addr );
1.134 sh4ptr_t sh4_get_region_by_vma( sh4addr_t addr );
1.135
1.136 -/* SH4 Support methods */
1.137 -uint32_t sh4_read_sr(void);
1.138 -void sh4_write_sr(uint32_t val);
1.139 +/* SH4 Exceptions */
1.140 +#define EXC_POWER_RESET 0x000 /* reset vector */
1.141 +#define EXC_MANUAL_RESET 0x020 /* reset vector */
1.142 +#define EXC_TLB_MISS_READ 0x040 /* TLB vector */
1.143 +#define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */
1.144 +#define EXC_INIT_PAGE_WRITE 0x080
1.145 +#define EXC_TLB_PROT_READ 0x0A0
1.146 +#define EXC_TLB_PROT_WRITE 0x0C0
1.147 +#define EXC_DATA_ADDR_READ 0x0E0
1.148 +#define EXC_DATA_ADDR_WRITE 0x100
1.149 +#define EXC_TLB_MULTI_HIT 0x140
1.150 +#define EXC_SLOT_ILLEGAL 0x1A0
1.151 +#define EXC_ILLEGAL 0x180
1.152 +#define EXC_TRAP 0x160
1.153 +#define EXC_FPU_DISABLED 0x800
1.154 +#define EXC_SLOT_FPU_DISABLED 0x820
1.155
1.156 -/* Peripheral functions */
1.157 -void CPG_reset( void );
1.158 -void TMU_run_slice( uint32_t );
1.159 -void TMU_update_clocks( void );
1.160 -void TMU_reset( void );
1.161 -void TMU_save_state( FILE * );
1.162 -int TMU_load_state( FILE * );
1.163 -void DMAC_reset( void );
1.164 -void DMAC_run_slice( uint32_t );
1.165 -void DMAC_save_state( FILE * );
1.166 -int DMAC_load_state( FILE * );
1.167 -void SCIF_reset( void );
1.168 -void SCIF_run_slice( uint32_t );
1.169 -void SCIF_save_state( FILE *f );
1.170 -int SCIF_load_state( FILE *f );
1.171 -void INTC_reset( void );
1.172 -void INTC_save_state( FILE *f );
1.173 -int INTC_load_state( FILE *f );
1.174 -void MMU_init( void );
1.175 -void MMU_reset( void );
1.176 -void MMU_save_state( FILE *f );
1.177 -int MMU_load_state( FILE *f );
1.178 -void MMU_ldtlb();
1.179 -void SCIF_update_line_speed(void);
1.180 +#define EXV_EXCEPTION 0x100 /* General exception vector */
1.181 +#define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
1.182 +#define EXV_INTERRUPT 0x600 /* External interrupt vector */
1.183 +
1.184 +gboolean sh4_raise_exception( int );
1.185 +gboolean sh4_raise_reset( int );
1.186 +gboolean sh4_raise_trap( int );
1.187 +gboolean sh4_raise_slot_exception( int, int );
1.188 +gboolean sh4_raise_tlb_exception( int );
1.189 +void sh4_accept_interrupt( void );
1.190
1.191 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
1.192 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
1.193 @@ -207,44 +165,6 @@
1.194 #define FPULf *((float *)&sh4r.fpul)
1.195 #define FPULi (sh4r.fpul)
1.196
1.197 -/* CPU-generated exception code/vector pairs */
1.198 -#define EXC_POWER_RESET 0x000 /* vector special */
1.199 -#define EXC_MANUAL_RESET 0x020
1.200 -#define EXC_TLB_MISS_READ 0x040
1.201 -#define EXC_TLB_MISS_WRITE 0x060
1.202 -#define EXC_INIT_PAGE_WRITE 0x080
1.203 -#define EXC_TLB_PROT_READ 0x0A0
1.204 -#define EXC_TLB_PROT_WRITE 0x0C0
1.205 -#define EXC_DATA_ADDR_READ 0x0E0
1.206 -#define EXC_DATA_ADDR_WRITE 0x100
1.207 -#define EXC_TLB_MULTI_HIT 0x140
1.208 -#define EXC_SLOT_ILLEGAL 0x1A0
1.209 -#define EXC_ILLEGAL 0x180
1.210 -#define EXC_TRAP 0x160
1.211 -#define EXC_FPU_DISABLED 0x800
1.212 -#define EXC_SLOT_FPU_DISABLED 0x820
1.213 -
1.214 -#define EXV_EXCEPTION 0x100 /* General exception vector */
1.215 -#define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
1.216 -#define EXV_INTERRUPT 0x600 /* External interrupt vector */
1.217 -
1.218 -/* Exceptions (for use with sh4_raise_exception) */
1.219 -
1.220 -#define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
1.221 -#define EX_SLOT_ILLEGAL 0x1A0, 0x100
1.222 -#define EX_TLB_MISS_READ 0x040, 0x400
1.223 -#define EX_TLB_MISS_WRITE 0x060, 0x400
1.224 -#define EX_INIT_PAGE_WRITE 0x080, 0x100
1.225 -#define EX_TLB_PROT_READ 0x0A0, 0x100
1.226 -#define EX_TLB_PROT_WRITE 0x0C0, 0x100
1.227 -#define EX_DATA_ADDR_READ 0x0E0, 0x100
1.228 -#define EX_DATA_ADDR_WRITE 0x100, 0x100
1.229 -#define EX_FPU_EXCEPTION 0x120, 0x100
1.230 -#define EX_TRAPA 0x160, 0x100
1.231 -#define EX_BREAKPOINT 0x1E0, 0x100
1.232 -#define EX_FPU_DISABLED 0x800, 0x100
1.233 -#define EX_SLOT_FPU_DISABLED 0x820, 0x100
1.234 -
1.235 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
1.236
1.237 #ifdef __cplusplus
.