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lxdream.org :: lxdream/src/aica/armcore.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/aica/armcore.c
changeset 59:dceb8ef1da55
prev52:429b7fc6b843
next63:be4fec751961
author nkeynes
date Mon Jan 02 14:49:29 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Change LDM in accordance with the second part of 5.4.6
Fix arm_raise_exception to actually work
file annotate diff log raw
1.1 --- a/src/aica/armcore.c Wed Dec 28 22:50:08 2005 +0000
1.2 +++ b/src/aica/armcore.c Mon Jan 02 14:49:29 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: armcore.c,v 1.13 2005-12-28 22:50:08 nkeynes Exp $
1.6 + * $Id: armcore.c,v 1.14 2006-01-02 14:49:29 nkeynes Exp $
1.7 *
1.8 * ARM7TDMI CPU emulation core.
1.9 *
1.10 @@ -211,7 +211,7 @@
1.11 arm_set_mode( mode );
1.12 armr.spsr = spsr;
1.13 armr.r[14] = armr.r[15];
1.14 - armr.cpsr = (spsr & (~CPSR_T)) | CPSR_I;
1.15 + armr.cpsr = (spsr & 0xFFFFFF00) | mode | CPSR_I;
1.16 if( mode == MODE_FIQ )
1.17 armr.cpsr |= CPSR_F;
1.18 armr.r[15] = arm_exceptions[exception][1];
1.19 @@ -658,8 +658,8 @@
1.20
1.21 gboolean arm_execute_instruction( void )
1.22 {
1.23 - uint32_t pc = PC;
1.24 - uint32_t ir = MEM_READ_LONG(pc);
1.25 + uint32_t pc;
1.26 + uint32_t ir;
1.27 uint32_t operand, operand2, tmp, tmp2, cond;
1.28
1.29 tmp = armr.int_pending & (~armr.cpsr);
1.30 @@ -671,7 +671,8 @@
1.31 }
1.32 }
1.33
1.34 - pc += 4;
1.35 + ir = MEM_READ_LONG(PC);
1.36 + pc = PC + 4;
1.37 PC = pc;
1.38
1.39 /**
1.40 @@ -1129,11 +1130,11 @@
1.41 } else { /* Load/store multiple */
1.42 int prestep, poststep;
1.43 if( PFLAG(ir) ) {
1.44 + prestep = UFLAG(ir) ? 4 : -4;
1.45 + poststep = 0 ;
1.46 + } else {
1.47 prestep = 0;
1.48 poststep = UFLAG(ir) ? 4 : -4;
1.49 - } else {
1.50 - prestep = UFLAG(ir) ? 4 : -4;
1.51 - poststep = 0 ;
1.52 }
1.53 operand = RN(ir);
1.54 if( BFLAG(ir) ) {
1.55 @@ -1148,6 +1149,8 @@
1.56 operand += poststep;
1.57 }
1.58 }
1.59 + if( WFLAG(ir) )
1.60 + LRN(ir) = operand;
1.61 arm_restore_cpsr();
1.62 if( armr.t ) PC &= 0xFFFFFFFE;
1.63 else PC &= 0xFFFFFFFC;
1.64 @@ -1211,9 +1214,9 @@
1.65 operand += poststep;
1.66 }
1.67 }
1.68 + if( WFLAG(ir) )
1.69 + LRN(ir) = operand;
1.70 }
1.71 - if( WFLAG(ir) )
1.72 - LRN(ir) = operand;
1.73 }
1.74 break;
1.75 case 3: /* Copro */
.