filename | test/sh4/tlb.s |
changeset | 586:2a3ba82cf243 |
next | 976:e57a25d9eb7d |
author | nkeynes |
date | Tue Aug 19 23:39:14 2008 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Fix testsh4x86 again |
file | annotate | diff | log | raw |
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00001.2 +++ b/test/sh4/tlb.s Tue Aug 19 23:39:14 2008 +00001.3 @@ -0,0 +1,165 @@1.4 +.section .text1.5 +.include "sh4/inc.s"1.6 +!1.7 +! Test for correct UTLB operation.1.8 +!1.9 +! Note we don't test triggering a TLB multiple-hit exception - it's a reset1.10 +! rather than a regular exception.1.11 +1.12 +.global _test_tlb1.13 +_test_tlb:1.14 + start_test1.15 +1.16 +! Turn on AT, and flush the current TLB (if any)1.17 +! Initialize to SV=0, SQMD=0, URB=URC=LRUI=01.18 + mov.l test_tlb_mmucr, r01.19 + mov #5, r11.20 + mov.l r1, @r01.21 +1.22 +! Privileged mode tests first (much easier)1.23 + add #1, r121.24 + mov.l test_tlb1_pteh, r11.25 + mov.l test_tlb_pteh, r21.26 + mov.l r1, @r21.27 + mov.l test_tlb1_ptel, r11.28 + mov.l test_tlb_ptel, r21.29 + mov.l r1, @r21.30 + ldtlb1.31 +1.32 +! Simple read1.33 + mov.l test_tlb1_direct, r31.34 + mov #42, r21.35 + mov.l r2, @r31.36 + mov.l test_tlb1_mmu, r01.37 + mov.l @r0, r11.38 + cmp/eq r1, r21.39 + bt test_tlb_21.40 + fail test_tlb_str_k1.41 + bra test_tlb_21.42 + nop1.43 +test_tlb1_pteh:1.44 + .long 0x123450121.45 +test_tlb1_ptel:1.46 + .long 0x005F81201.47 +1.48 +test_tlb_2:1.49 + ! Trigger an initial-page-write exception1.50 + add #1, r121.51 + expect_exc 0x000000801.52 + mov.l test_tlb1_mmu, r01.53 +test_tlb2_exc:1.54 + mov.l r0, @r01.55 + assert_tlb_exc_caught test_tlb_str_k test_tlb2_exc test_tlb1_mmu1.56 +1.57 +test_tlb_3:1.58 + ! Trigger a missing page read exception by invalidation1.59 + add #1, r121.60 + mov.l test_tlb3_addr, r11.61 + mov.l test_tlb3_data, r21.62 + mov.l r2, @r11.63 +1.64 + expect_exc 0x000000401.65 + mov.l test_tlb1_mmu, r01.66 +test_tlb3_exc:1.67 + mov.l @r0, r21.68 + assert_tlb_exc_caught test_tlb_str_k, test_tlb3_exc, test_tlb1_mmu1.69 + bra test_tlb_41.70 + nop1.71 +1.72 +test_tlb3_addr:1.73 + .long 0xF6000F801.74 +test_tlb3_data:1.75 + .long 0x123452121.76 +1.77 +test_tlb_4:1.78 + ! Test missing page write exception on the same page1.79 + add #1, r121.80 + expect_exc 0x000000601.81 + mov.l test_tlb1_mmu, r01.82 +test_tlb4_exc:1.83 + mov.l r2, @r01.84 + assert_tlb_exc_caught test_tlb_str_k, test_tlb4_exc, test_tlb1_mmu1.85 +1.86 +test_tlb_5: ! Test initial write exception1.87 + add #1, r121.88 +1.89 + mov.l test_tlb5_addr, r11.90 + mov.l test_tlb5_data, r21.91 + mov.l r2, @r11.92 +1.93 + expect_exc 0x000000801.94 + mov.l test_tlb1_mmu, r01.95 + mov #63, r31.96 +test_tlb5_exc:1.97 + mov.l r3, @r01.98 + assert_tlb_exc_caught test_tlb_str_k, test_tlb5_exc, test_tlb1_mmu1.99 + mov.l test_tlb1_direct, r31.100 + mov.l @r3, r41.101 + mov #42, r21.102 + cmp/eq r2, r41.103 + bf test_tlb5_fail1.104 + mov.l test_tlb1_mmu, r01.105 + mov.l @r0, r31.106 + cmp/eq r2, r31.107 + bt test_tlb_61.108 +test_tlb5_fail:1.109 + fail test_tlb_str_k1.110 +1.111 +test_tlb5_addr:1.112 + .long 0xF60000001.113 +test_tlb5_data:1.114 + .long 0x123451121.115 +1.116 +test_tlb_6:! Test successful write.1.117 + add #1, r121.118 +1.119 + mov.l test_tlb6_addr, r11.120 + mov.l test_tlb6_data, r21.121 + mov.l r2, @r11.122 +1.123 + mov.l test_tlb1_mmu, r01.124 + mov #77, r31.125 + mov.l r3, @r01.126 + mov.l test_tlb1_direct, r11.127 + mov.l @r1, r21.128 + cmp/eq r2, r31.129 + bt test_tlb_71.130 + fail test_tlb_str_k1.131 + bra test_tlb_71.132 + nop1.133 +1.134 +test_tlb_7:1.135 + bra test_tlb_end1.136 + nop1.137 +1.138 +test_tlb6_addr:1.139 + .long 0xF6000F801.140 +test_tlb6_data:1.141 + .long 0x123453121.142 +1.143 +1.144 +test_tlb1_mmu:1.145 + .long 0x123450401.146 +test_tlb1_direct:1.147 + .long 0xA05F8040 ! Display border colour1.148 +1.149 +test_tlb_end:1.150 + xor r0, r01.151 + mov.l test_tlb_mmucr, r11.152 + mov.l r0, @r11.153 +1.154 + end_test test_tlb_str_k1.155 +1.156 +test_tlb_mmucr:1.157 + .long 0xFF0000101.158 +test_tlb_pteh:1.159 + .long 0xFF0000001.160 +test_tlb_ptel:1.161 + .long 0xFF0000041.162 +test_tlb_tea:1.163 + .long 0xFF00000C1.164 +test_tlb_str:1.165 + .string "TLB"1.166 +.align 41.167 +test_tlb_str_k:1.168 + .long test_tlb_str
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