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lxdream.org :: lxdream/src/pvr2/pvr2.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 191:df4441cf3128
prev189:615b70cfd729
next193:31151fcc3cb7
author nkeynes
date Wed Aug 02 06:24:08 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add more register masks (in line with test case)
Rename renderer registers for consistency
file annotate diff log raw
1.1 --- a/src/pvr2/pvr2.c Wed Aug 02 04:06:45 2006 +0000
1.2 +++ b/src/pvr2/pvr2.c Wed Aug 02 06:24:08 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: pvr2.c,v 1.28 2006-08-02 04:06:45 nkeynes Exp $
1.6 + * $Id: pvr2.c,v 1.29 2006-08-02 06:24:08 nkeynes Exp $
1.7 *
1.8 * PVR2 (Video) Core module implementation and MMIO registers.
1.9 *
1.10 @@ -222,10 +222,31 @@
1.11 case TA_LISTPOS:
1.12 /* Readonly registers */
1.13 break;
1.14 - case RENDSTART:
1.15 + case RENDER_START:
1.16 if( val == 0xFFFFFFFF )
1.17 pvr2_render_scene();
1.18 break;
1.19 + case PVRUNK1:
1.20 + MMIO_WRITE( PVR2, reg, val&0x000007FF );
1.21 + break;
1.22 + case RENDER_POLYBASE:
1.23 + MMIO_WRITE( PVR2, reg, val&0x00F00000 );
1.24 + break;
1.25 + case RENDER_TSPCFG:
1.26 + MMIO_WRITE( PVR2, reg, val&0x00010101 );
1.27 + break;
1.28 + case DISPBORDER:
1.29 + MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
1.30 + break;
1.31 + case DISPMODE:
1.32 + MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
1.33 + break;
1.34 + case RENDER_MODE:
1.35 + MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
1.36 + break;
1.37 + case RENDER_SIZE:
1.38 + MMIO_WRITE( PVR2, reg, val&0x000001FF );
1.39 + break;
1.40 case DISPADDR1:
1.41 val &= 0x00FFFFFC;
1.42 MMIO_WRITE( PVR2, reg, val );
1.43 @@ -234,14 +255,24 @@
1.44 pvr2_state.retrace = FALSE;
1.45 }
1.46 break;
1.47 - case HCLIP:
1.48 - MMIO_WRITE( PVR2, reg, val & 0x07FF07FF );
1.49 + case DISPADDR2:
1.50 + MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
1.51 + break;
1.52 + case DISPSIZE:
1.53 + MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
1.54 + break;
1.55 + case RENDER_ADDR1:
1.56 + case RENDER_ADDR2:
1.57 + MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
1.58 + break;
1.59 + case RENDER_HCLIP:
1.60 + MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
1.61 break;
1.62 - case VCLIP:
1.63 - MMIO_WRITE( PVR2, reg, val & 0x03FF03FF );
1.64 + case RENDER_VCLIP:
1.65 + MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
1.66 break;
1.67 case HPOS_IRQ:
1.68 - MMIO_WRITE( PVR2, reg, val & 0x03FF33FF );
1.69 + MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
1.70 break;
1.71 case VPOS_IRQ:
1.72 val = val & 0x03FF03FF;
1.73 @@ -249,26 +280,48 @@
1.74 pvr2_state.irq_vpos2 = val & 0x03FF;
1.75 MMIO_WRITE( PVR2, reg, val );
1.76 break;
1.77 + case RENDER_SHADOW:
1.78 + MMIO_WRITE( PVR2, reg, val&0x000001FF );
1.79 + break;
1.80 + case RENDER_OBJCFG:
1.81 + MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
1.82 + break;
1.83 + case RENDER_TSPCLIP:
1.84 + MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
1.85 + break;
1.86 + case RENDER_BGPLANE:
1.87 + MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
1.88 + break;
1.89 + case RENDER_ISPCFG:
1.90 + MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
1.91 + break;
1.92 case TA_TILEBASE:
1.93 case TA_TILEEND:
1.94 case TA_LISTBASE:
1.95 - MMIO_WRITE( PVR2, reg, val & 0x00FFFFE0 );
1.96 + MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
1.97 break;
1.98 + case RENDER_TILEBASE:
1.99 case TA_POLYBASE:
1.100 case TA_POLYEND:
1.101 - MMIO_WRITE( PVR2, reg, val & 0x00FFFFFC );
1.102 + MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
1.103 break;
1.104 case TA_TILESIZE:
1.105 - MMIO_WRITE( PVR2, reg, val & 0x000F003F );
1.106 + MMIO_WRITE( PVR2, reg, val&0x000F003F );
1.107 break;
1.108 case TA_TILECFG:
1.109 - MMIO_WRITE( PVR2, reg, val & 0x00133333 );
1.110 + MMIO_WRITE( PVR2, reg, val&0x00133333 );
1.111 break;
1.112 case TA_INIT:
1.113 if( val & 0x80000000 )
1.114 pvr2_ta_init();
1.115 break;
1.116
1.117 + /* Nonexistent registers (as far as we know, anyway) */
1.118 + case 0x01C:
1.119 + case 0x024:
1.120 + case 0x028:
1.121 + case 0x058:
1.122 + break;
1.123 default:
1.124 MMIO_WRITE( PVR2, reg, val );
1.125 }
.