1.1 --- a/src/aica/aica.c Mon Dec 26 11:52:56 2005 +0000
1.2 +++ b/src/aica/aica.c Mon Jan 02 14:50:12 2006 +0000
1.5 - * $Id: aica.c,v 1.9 2005-12-26 11:52:56 nkeynes Exp $
1.6 + * $Id: aica.c,v 1.10 2006-01-02 14:50:12 nkeynes Exp $
1.8 * This is the core sound system (ie the bit which does the actual work)
1.14 +#include "armcore.h"
1.19 return arm_load_state( f );
1.22 +int aica_event_pending = 0;
1.23 +int aica_clear_count = 0;
1.25 +/* Note: This is probably not necessarily technically correct but it should
1.26 + * work in the meantime.
1.29 +void aica_event( int event )
1.31 + if( aica_event_pending == 0 )
1.32 + armr.int_pending |= CPSR_F;
1.33 + aica_event_pending |= (1<<event);
1.35 + int pending = MMIO_READ( AICA2, AICA_IRQ );
1.36 + if( pending == 0 || event < pending )
1.37 + MMIO_WRITE( AICA2, AICA_IRQ, event );
1.40 +void aica_clear_event( )
1.42 + aica_clear_count++;
1.43 + if( aica_clear_count == 4 ) {
1.45 + aica_clear_count = 0;
1.47 + for( i=0; i<8; i++ ) {
1.48 + if( aica_event_pending & (1<<i) ) {
1.49 + aica_event_pending &= ~(1<<i);
1.53 + for( ;i<8; i++ ) {
1.54 + if( aica_event_pending & (1<<i) ) {
1.55 + MMIO_WRITE( AICA2, AICA_IRQ, i );
1.59 + if( aica_event_pending == 0 )
1.60 + armr.int_pending &= ~CPSR_F;
1.63 /** Channel register structure:
1.64 * 00 4 Channel config
1.65 * 04 4 Waveform address lo (16 bits)
1.68 MMIO_WRITE( AICA2, AICA_RESET, val );
1.70 + case AICA_IRQCLEAR:
1.71 + aica_clear_event();
1.74 MMIO_WRITE( AICA2, reg, val );