filename | src/aica/armcore.h |
changeset | 51:ed6c27067502 |
prev | 46:30d123047e16 |
next | 66:2ec5b6eb75e5 |
author | nkeynes |
date | Wed Dec 28 22:49:26 2005 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Add several missing M instructions Add SWI instruction Fix disasm of LDM Accept interrupts |
file | annotate | diff | log | raw |
1.1 --- a/src/aica/armcore.h Tue Dec 27 08:42:57 2005 +00001.2 +++ b/src/aica/armcore.h Wed Dec 28 22:49:26 2005 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: armcore.h,v 1.10 2005-12-27 08:42:57 nkeynes Exp $1.6 + * $Id: armcore.h,v 1.11 2005-12-28 22:49:26 nkeynes Exp $1.7 *1.8 * Interface definitions for the ARM CPU emulation core proper.1.9 *1.10 @@ -49,6 +49,7 @@1.11 uint32_t c,n,z,v,t;1.13 /* "fake" registers */1.14 + uint32_t int_pending; /* Mask of CPSR_I and CPSR_F */1.15 uint32_t shift_c; /* used for temporary storage of shifter results */1.16 uint32_t icount; /* Instruction counter */1.17 };
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