1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/src/asic.c	Sat Mar 13 00:03:32 2004 +0000
     1.3 @@ -0,0 +1,105 @@
     1.4 +#include <assert.h>
     1.5 +#include "dream.h"
     1.6 +#include "mem.h"
     1.7 +#include "sh4/intc.h"
     1.8 +#include "asic.h"
     1.9 +#include "maple.h"
    1.10 +#define MMIO_IMPL
    1.11 +#include "asic.h"
    1.12 +/*
    1.13 + * Open questions:
    1.14 + *   1) Does changing the mask after event occurance result in the
    1.15 + *      interrupt being delivered immediately?
    1.16 + *   2) If the pending register is not cleared after an interrupt, does
    1.17 + *      the interrupt line remain high? (ie does the IRQ reoccur?)
    1.18 + * TODO: Logic diagram of ASIC event/interrupt logic.
    1.19 + *
    1.20 + * ... don't even get me started on the "EXTDMA" page, about which, apparently,
    1.21 + * practically nothing is publicly known...
    1.22 + */
    1.23 +
    1.24 +void asic_init( void )
    1.25 +{
    1.26 +    register_io_region( &mmio_region_ASIC );
    1.27 +    register_io_region( &mmio_region_EXTDMA );
    1.28 +    mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
    1.29 +    asic_event( EVENT_GDROM_CMD );
    1.30 +}
    1.31 +
    1.32 +void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
    1.33 +{
    1.34 +    switch( reg ) {
    1.35 +        case PIRQ0:
    1.36 +        case PIRQ1:
    1.37 +        case PIRQ2:
    1.38 +            /* Clear any interrupts */
    1.39 +            MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
    1.40 +            break;
    1.41 +        case MAPLE_STATE:
    1.42 +            MMIO_WRITE( ASIC, reg, val );
    1.43 +            if( val & 1 ) {
    1.44 +                uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
    1.45 +//                maple_handle_buffer( maple_addr );
    1.46 +		WARN( "Maple request initiated, halting" );
    1.47 +                MMIO_WRITE( ASIC, reg, 0 );
    1.48 +                sh4_stop();
    1.49 +            }
    1.50 +            break;
    1.51 +        default:
    1.52 +            MMIO_WRITE( ASIC, reg, val );
    1.53 +            WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
    1.54 +                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
    1.55 +    }
    1.56 +}
    1.57 +
    1.58 +int32_t mmio_region_ASIC_read( uint32_t reg )
    1.59 +{
    1.60 +    int32_t val;
    1.61 +    switch( reg ) {
    1.62 +        case PIRQ0:
    1.63 +        case PIRQ1:
    1.64 +        case PIRQ2:
    1.65 +            val = MMIO_READ(ASIC, reg);
    1.66 +//            WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
    1.67 +//                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
    1.68 +            return val;            
    1.69 +        case G2STATUS:
    1.70 +            return 0; /* find out later if there's any cases we actually need to care about */
    1.71 +        default:
    1.72 +            val = MMIO_READ(ASIC, reg);
    1.73 +            WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
    1.74 +                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
    1.75 +            return val;
    1.76 +    }
    1.77 +           
    1.78 +}
    1.79 +
    1.80 +void asic_event( int event )
    1.81 +{
    1.82 +    int offset = ((event&0x60)>>3);
    1.83 +    int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
    1.84 +
    1.85 +    if( result & MMIO_READ(ASIC, IRQA0 + offset) )
    1.86 +        intc_raise_interrupt( INT_IRQ13 );
    1.87 +    if( result & MMIO_READ(ASIC, IRQB0 + offset) )
    1.88 +        intc_raise_interrupt( INT_IRQ11 );
    1.89 +    if( result & MMIO_READ(ASIC, IRQC0 + offset) )
    1.90 +        intc_raise_interrupt( INT_IRQ9 );
    1.91 +}
    1.92 +
    1.93 +
    1.94 +
    1.95 +MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
    1.96 +{
    1.97 +    MMIO_WRITE( EXTDMA, reg, val );
    1.98 +}
    1.99 +
   1.100 +MMIO_REGION_READ_FN( EXTDMA, reg )
   1.101 +{
   1.102 +    switch( reg ) {
   1.103 +        case GDBUSY: return 0;
   1.104 +        default:
   1.105 +            return MMIO_READ( EXTDMA, reg );
   1.106 +    }
   1.107 +}
   1.108 +