Search
lxdream.org :: lxdream/src/pvr2/pvr2.c :: diff
lxdream 0.9.1
released Jun 29
Download Now
filename src/pvr2/pvr2.c
changeset 1:eea311cfd33e
next2:42349f6ea216
author nkeynes
date Sat Mar 13 00:03:32 2004 +0000 (17 years ago)
permissions -rw-r--r--
last change This commit was generated by cvs2svn to compensate for changes in r2,
which included commits to RCS files with non-trunk default branches.
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/pvr2/pvr2.c Sat Mar 13 00:03:32 2004 +0000
1.3 @@ -0,0 +1,96 @@
1.4 +#include "dream.h"
1.5 +#include "video.h"
1.6 +#include "mem.h"
1.7 +#include "asic.h"
1.8 +#include "pvr2.h"
1.9 +#define MMIO_IMPL
1.10 +#include "pvr2.h"
1.11 +
1.12 +char *video_base;
1.13 +
1.14 +void pvr2_init( void )
1.15 +{
1.16 + register_io_region( &mmio_region_PVR2 );
1.17 + video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
1.18 +}
1.19 +
1.20 +uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
1.21 +int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
1.22 +char *frame_start; /* current video start address (in real memory) */
1.23 +
1.24 +/*
1.25 + * Display the next frame, copying the current contents of video ram to
1.26 + * the window. If the video configuration has changed, first recompute the
1.27 + * new frame size/depth.
1.28 + */
1.29 +void pvr2_next_frame( void )
1.30 +{
1.31 + if( bChanged ) {
1.32 + int dispsize = MMIO_READ( PVR2, DISPSIZE );
1.33 + int dispmode = MMIO_READ( PVR2, DISPMODE );
1.34 + int vidcfg = MMIO_READ( PVR2, VIDCFG );
1.35 + vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
1.36 + vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
1.37 + vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
1.38 + vid_col = (dispmode & DISPMODE_COL);
1.39 + frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
1.40 + interlaced = (vidcfg & VIDCFG_I ? 1 : 0);
1.41 + bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & VIDCFG_VO ) ? 1 : 0;
1.42 + vid_size = (vid_ppl * vid_lpf) << (interlaced ? 3 : 2);
1.43 + vid_hres = vid_ppl;
1.44 + vid_vres = vid_lpf;
1.45 + if( interlaced ) vid_vres <<= 1;
1.46 + switch( vid_col ) {
1.47 + case MODE_RGB15:
1.48 + case MODE_RGB16: vid_hres <<= 1; break;
1.49 + case MODE_RGB24: vid_hres *= 3; break;
1.50 + case MODE_RGB32: vid_hres <<= 2; break;
1.51 + }
1.52 + vid_hres >>= 2;
1.53 + video_update_size( vid_hres, vid_vres, vid_col );
1.54 + bChanged = 0;
1.55 + }
1.56 + if( bEnabled ) {
1.57 + /* Assume bit depths match for now... */
1.58 + memcpy( video_data, frame_start, vid_size );
1.59 + } else {
1.60 + memset( video_data, 0, vid_size );
1.61 + }
1.62 + video_update_frame();
1.63 + asic_event( EVENT_SCANLINE1 );
1.64 + asic_event( EVENT_SCANLINE2 );
1.65 + asic_event( EVENT_RETRACE );
1.66 +}
1.67 +
1.68 +void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
1.69 +{
1.70 + if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
1.71 + MMIO_WRITE( PVR2, reg, val );
1.72 + /* I don't want to hear about these */
1.73 + return;
1.74 + }
1.75 +
1.76 + INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val,
1.77 + MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
1.78 +
1.79 + switch(reg) {
1.80 + case DISPSIZE: bChanged = 1;
1.81 + case DISPMODE: bChanged = 1;
1.82 + case DISPADDR1: bChanged = 1;
1.83 + case DISPADDR2: bChanged = 1;
1.84 + case VIDCFG: bChanged = 1;
1.85 + break;
1.86 +
1.87 + }
1.88 + MMIO_WRITE( PVR2, reg, val );
1.89 +}
1.90 +
1.91 +MMIO_REGION_READ_FN( PVR2, reg )
1.92 +{
1.93 + switch( reg ) {
1.94 + case BEAMPOS:
1.95 + return sh4r.icount&0x20 ? 0x2000 : 0;
1.96 + default:
1.97 + return MMIO_READ( PVR2, reg );
1.98 + }
1.99 +}
.