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lxdream.org :: lxdream/src/sh4/mem.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/mem.h
changeset 1:eea311cfd33e
next2:42349f6ea216
author nkeynes
date Sat Mar 13 00:03:32 2004 +0000 (15 years ago)
permissions -rw-r--r--
last change This commit was generated by cvs2svn to compensate for changes in r2,
which included commits to RCS files with non-trunk default branches.
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/sh4/mem.h Sat Mar 13 00:03:32 2004 +0000
1.3 @@ -0,0 +1,85 @@
1.4 +#ifndef dream_sh4_mem_H
1.5 +#define dream_sh4_mem_H
1.6 +
1.7 +#include <stdint.h>
1.8 +#include "sh4mmio.h"
1.9 +
1.10 +#ifdef __cplusplus
1.11 +extern "C" {
1.12 +#if 0
1.13 +}
1.14 +#endif
1.15 +#endif
1.16 +
1.17 +struct mem_region {
1.18 + uint32_t base;
1.19 + uint32_t size;
1.20 + char *name;
1.21 + char *mem;
1.22 + int flags;
1.23 +};
1.24 +
1.25 +#define MAX_IO_REGIONS 24
1.26 +#define MAX_MEM_REGIONS 8
1.27 +
1.28 +#define MEM_REGION_MAIN "System RAM"
1.29 +#define MEM_REGION_VIDEO "Video RAM"
1.30 +#define MEM_REGION_AUDIO "Audio RAM"
1.31 +#define MEM_REGION_AUDIO_SCRATCH "Audio Scratch RAM"
1.32 +
1.33 +#define MB * (1024 * 1024)
1.34 +#define KB * 1024
1.35 +
1.36 +int32_t mem_read_long( uint32_t addr );
1.37 +int32_t mem_read_word( uint32_t addr );
1.38 +int32_t mem_read_byte( uint32_t addr );
1.39 +void mem_write_long( uint32_t addr, uint32_t val );
1.40 +void mem_write_word( uint32_t addr, uint32_t val );
1.41 +void mem_write_byte( uint32_t addr, uint32_t val );
1.42 +
1.43 +int32_t mem_read_phys_word( uint32_t addr );
1.44 +void *mem_create_ram_region( uint32_t base, uint32_t size, char *name );
1.45 +void *mem_load_rom( char *name, uint32_t base, uint32_t size, uint32_t crc );
1.46 +char *mem_get_region( uint32_t addr );
1.47 +char *mem_get_region_by_name( char *name );
1.48 +void mem_set_cache_mode( int );
1.49 +int mem_has_page( uint32_t addr );
1.50 +
1.51 +void mem_init( void );
1.52 +void mem_reset( void );
1.53 +
1.54 +
1.55 +/* mmucr register bits */
1.56 +#define MMUCR_AT 0x00000001 /* Address Translation enabled */
1.57 +#define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */
1.58 +#define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
1.59 +#define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
1.60 +#define MMUCR_URC 0x0000FC00 /* UTLB access counter */
1.61 +#define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */
1.62 +#define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
1.63 +#define MMUCR_MASK 0xFCFCFF05
1.64 +#define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
1.65 +
1.66 +#define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
1.67 +
1.68 +/* ccr register bits */
1.69 +#define CCR_IIX 0x00008000 /* IC index enable */
1.70 +#define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */
1.71 +#define CCR_ICE 0x00000100 /* IC enable */
1.72 +#define CCR_OIX 0x00000080 /* OC index enable */
1.73 +#define CCR_ORA 0x00000020 /* OC RAM enable */
1.74 +#define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */
1.75 +#define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */
1.76 +#define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */
1.77 +#define CCR_OCE 0x00000001 /* OC enable */
1.78 +#define CCR_MASK 0x000089AF
1.79 +#define CCR_RMASK 0x000081A7 /* Read mask */
1.80 +
1.81 +#define MEM_OC_DISABLED 0
1.82 +#define MEM_OC_INDEX0 CCR_ORA
1.83 +#define MEM_OC_INDEX1 CCR_ORA|CCR_OIX
1.84 +
1.85 +#ifdef __cplusplus
1.86 +}
1.87 +#endif
1.88 +#endif
.