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lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 1:eea311cfd33e
next2:42349f6ea216
author nkeynes
date Sat Mar 13 00:03:32 2004 +0000 (16 years ago)
permissions -rw-r--r--
last change This commit was generated by cvs2svn to compensate for changes in r2,
which included commits to RCS files with non-trunk default branches.
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/sh4/sh4core.c Sat Mar 13 00:03:32 2004 +0000
1.3 @@ -0,0 +1,1110 @@
1.4 +#include <math.h>
1.5 +#include "dream.h"
1.6 +#include "sh4core.h"
1.7 +#include "sh4mmio.h"
1.8 +#include "mem.h"
1.9 +#include "intc.h"
1.10 +
1.11 +struct sh4_registers sh4r;
1.12 +
1.13 +static int running = 0;
1.14 +
1.15 +void sh4_init(void)
1.16 +{
1.17 + register_io_regions( mmio_list_sh4mmio );
1.18 +}
1.19 +
1.20 +void sh4_reset(void)
1.21 +{
1.22 + sh4r.pc = 0xA0000000;
1.23 + sh4r.new_pc= 0xA0000002;
1.24 + sh4r.vbr = 0x00000000;
1.25 + sh4r.fpscr = 0x00040001;
1.26 + sh4r.sr = 0x700000F0;
1.27 + sh4r.icount= 0;
1.28 + /* Everything else is undefined anyway, so don't bother setting it */
1.29 + intc_reset();
1.30 +}
1.31 +
1.32 +void sh4_set_pc( int pc )
1.33 +{
1.34 + sh4r.pc = pc;
1.35 + sh4r.new_pc = pc+2;
1.36 +}
1.37 +
1.38 +void sh4_stop(void)
1.39 +{
1.40 + running = 0;
1.41 +}
1.42 +
1.43 +void sh4_run(void)
1.44 +{
1.45 + running = 1;
1.46 + while( running ) {
1.47 + sh4_execute_instruction();
1.48 + }
1.49 +}
1.50 +
1.51 +void sh4_runfor(uint32_t count)
1.52 +{
1.53 + running = 1;
1.54 + while( running && count--) {
1.55 + sh4_execute_instruction();
1.56 + }
1.57 +}
1.58 +
1.59 +int sh4_isrunning(void)
1.60 +{
1.61 + return running;
1.62 +}
1.63 +
1.64 +void sh4_runto( uint32_t target_pc, uint32_t count )
1.65 +{
1.66 + running = 1;
1.67 + do {
1.68 + sh4_execute_instruction();
1.69 + } while( running && sh4r.pc != target_pc && count-- );
1.70 + if( count == 0 )
1.71 + running = 0;
1.72 +}
1.73 +
1.74 +#define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
1.75 +#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); return; }while(0)
1.76 +
1.77 +#define RAISE( x, v ) do{ \
1.78 + if( sh4r.vbr == 0 ) { \
1.79 + ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
1.80 + sh4_stop(); \
1.81 + } else { \
1.82 + sh4r.spc = sh4r.pc + 2; \
1.83 + sh4r.ssr = sh4_read_sr(); \
1.84 + sh4r.sgr = sh4r.r[15]; \
1.85 + MMIO_WRITE(MMU,EXPEVT,x); \
1.86 + sh4r.pc = sh4r.vbr + v; \
1.87 + sh4r.new_pc = sh4r.pc + 2; \
1.88 + sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
1.89 + } \
1.90 + return; } while(0)
1.91 +
1.92 +#define MEM_READ_BYTE( addr ) mem_read_byte(addr)
1.93 +#define MEM_READ_WORD( addr ) mem_read_word(addr)
1.94 +#define MEM_READ_LONG( addr ) mem_read_long(addr)
1.95 +#define MEM_WRITE_BYTE( addr, val ) mem_write_byte(addr, val)
1.96 +#define MEM_WRITE_WORD( addr, val ) mem_write_word(addr, val)
1.97 +#define MEM_WRITE_LONG( addr, val ) mem_write_long(addr, val)
1.98 +
1.99 +#define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
1.100 + ((uint32_t *)FR)[(reg)&0xE0] = mem_read_long(addr); \
1.101 + ((uint32_t *)FR)[(reg)|1] = mem_read_long(addr+4); \
1.102 +} else ((uint32_t *)FR)[reg] = mem_read_long(addr)
1.103 +
1.104 +#define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
1.105 + mem_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
1.106 + mem_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
1.107 +} else mem_write_long( addr, ((uint32_t *)FR)[reg] )
1.108 +
1.109 +#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
1.110 +
1.111 +#define EXC_POWER_RESET 0x000 /* vector special */
1.112 +#define EXC_MANUAL_RESET 0x020
1.113 +#define EXC_ILLEGAL 0x180
1.114 +#define EXV_ILLEGAL 0x100
1.115 +#define EXC_TRAP 0x160
1.116 +#define EXV_TRAP 0x100
1.117 +#define EXC_FPDISABLE 0x800
1.118 +#define EXV_FPDISABLE 0x100
1.119 +
1.120 +#define CHECK( x, c, v ) if( !x ) RAISE( c, v )
1.121 +#define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
1.122 +#define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
1.123 +#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
1.124 +
1.125 +static void sh4_switch_banks( )
1.126 +{
1.127 + uint32_t tmp[8];
1.128 +
1.129 + memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
1.130 + memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
1.131 + memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
1.132 +}
1.133 +
1.134 +static void sh4_load_sr( uint32_t newval )
1.135 +{
1.136 + if( (newval ^ sh4r.sr) & SR_RB )
1.137 + sh4_switch_banks();
1.138 + sh4r.sr = newval;
1.139 + sh4r.t = (newval&SR_T) ? 1 : 0;
1.140 + sh4r.s = (newval&SR_S) ? 1 : 0;
1.141 + sh4r.m = (newval&SR_M) ? 1 : 0;
1.142 + sh4r.q = (newval&SR_Q) ? 1 : 0;
1.143 + intc_mask_changed();
1.144 +}
1.145 +
1.146 +static uint32_t sh4_read_sr( void )
1.147 +{
1.148 + /* synchronize sh4r.sr with the various bitflags */
1.149 + sh4r.sr &= SR_MQSTMASK;
1.150 + if( sh4r.t ) sh4r.sr |= SR_T;
1.151 + if( sh4r.s ) sh4r.sr |= SR_S;
1.152 + if( sh4r.m ) sh4r.sr |= SR_M;
1.153 + if( sh4r.q ) sh4r.sr |= SR_Q;
1.154 + return sh4r.sr;
1.155 +}
1.156 +/* function for external use */
1.157 +void sh4_raise_exception( int code, int vector )
1.158 +{
1.159 + RAISE(code, vector);
1.160 +}
1.161 +
1.162 +static void sh4_accept_interrupt( void )
1.163 +{
1.164 + uint32_t code = intc_accept_interrupt();
1.165 +
1.166 + sh4r.ssr = sh4_read_sr();
1.167 + sh4r.spc = sh4r.pc;
1.168 + sh4r.sgr = sh4r.r[15];
1.169 + sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
1.170 + MMIO_WRITE( MMU, INTEVT, code );
1.171 + sh4r.pc = sh4r.vbr + 0x600;
1.172 + sh4r.new_pc = sh4r.pc + 2;
1.173 +}
1.174 +
1.175 +void sh4_execute_instruction( void )
1.176 +{
1.177 + int pc = sh4r.pc;
1.178 + unsigned short ir = MEM_READ_WORD(pc);
1.179 + uint32_t tmp;
1.180 + uint64_t tmpl;
1.181 +
1.182 +#define R0 sh4r.r[0]
1.183 +#define FR0 (FR[0])
1.184 +#define RN(ir) sh4r.r[(ir&0x0F00)>>8]
1.185 +#define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
1.186 +#define RM(ir) sh4r.r[(ir&0x00F0)>>4]
1.187 +#define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
1.188 +#define DISP8(ir) (ir&0x00FF)
1.189 +#define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
1.190 +#define IMM8(ir) SIGNEXT8(ir&0x00FF)
1.191 +#define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
1.192 +#define DISP12(ir) SIGNEXT12(ir&0x0FFF)
1.193 +#define FVN(ir) ((ir&0x0C00)
1.194 +#define FVM(ir) ((ir&0x0300)>>8)
1.195 +#define FRN(ir) (FR[(ir&0x0F00)>>8])
1.196 +#define FRM(ir) (FR[(ir&0x00F0)>>4])
1.197 +#define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
1.198 +#define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
1.199 +#define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
1.200 +#define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
1.201 +#define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
1.202 +#define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
1.203 +#define FRNn(ir) ((ir&0x0F00)>>8)
1.204 +#define FRMn(ir) ((ir&0x00F0)>>4)
1.205 +#define FPULf *((float *)&sh4r.fpul)
1.206 +#define FPULi (sh4r.fpul)
1.207 +
1.208 + if( SH4_INT_PENDING() ) sh4_accept_interrupt();
1.209 +
1.210 + sh4r.icount++;
1.211 +
1.212 + switch( (ir&0xF000)>>12 ) {
1.213 + case 0: /* 0000nnnnmmmmxxxx */
1.214 + switch( ir&0x000F ) {
1.215 + case 2:
1.216 + switch( (ir&0x00F0)>>4 ) {
1.217 + case 0: /* STC SR, Rn */
1.218 + CHECKPRIV();
1.219 + RN(ir) = sh4_read_sr();
1.220 + break;
1.221 + case 1: /* STC GBR, Rn */
1.222 + RN(ir) = sh4r.gbr;
1.223 + break;
1.224 + case 2: /* STC VBR, Rn */
1.225 + CHECKPRIV();
1.226 + RN(ir) = sh4r.vbr;
1.227 + break;
1.228 + case 3: /* STC SSR, Rn */
1.229 + CHECKPRIV();
1.230 + RN(ir) = sh4r.ssr;
1.231 + break;
1.232 + case 4: /* STC SPC, Rn */
1.233 + CHECKPRIV();
1.234 + RN(ir) = sh4r.spc;
1.235 + break;
1.236 + case 8: case 9: case 10: case 11: case 12: case 13:
1.237 + case 14: case 15:/* STC Rm_bank, Rn */
1.238 + CHECKPRIV();
1.239 + RN(ir) = RN_BANK(ir);
1.240 + break;
1.241 + default: UNDEF(ir);
1.242 + }
1.243 + break;
1.244 + case 3:
1.245 + switch( (ir&0x00F0)>>4 ) {
1.246 + case 0: /* BSRF Rn */
1.247 + CHECKDEST( pc + 4 + RN(ir) );
1.248 + sh4r.pr = sh4r.pc + 4;
1.249 + sh4r.pc = sh4r.new_pc;
1.250 + sh4r.new_pc = pc + 4 + RN(ir);
1.251 + return;
1.252 + case 2: /* BRAF Rn */
1.253 + CHECKDEST( pc + 4 + RN(ir) );
1.254 + sh4r.pc = sh4r.new_pc;
1.255 + sh4r.new_pc = pc + 4 + RN(ir);
1.256 + return;
1.257 + case 8: /* PREF [Rn] */
1.258 + case 9: /* OCBI [Rn] */
1.259 + case 10:/* OCBP [Rn] */
1.260 + case 11:/* OCBWB [Rn] */
1.261 + /* anything? */
1.262 + break;
1.263 + case 12:/* MOVCA.L R0, [Rn] */
1.264 + UNIMP(ir);
1.265 + default: UNDEF(ir);
1.266 + }
1.267 + break;
1.268 + case 4: /* MOV.B Rm, [R0 + Rn] */
1.269 + MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
1.270 + break;
1.271 + case 5: /* MOV.W Rm, [R0 + Rn] */
1.272 + MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
1.273 + break;
1.274 + case 6: /* MOV.L Rm, [R0 + Rn] */
1.275 + MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
1.276 + break;
1.277 + case 7: /* MUL.L Rm, Rn */
1.278 + sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000) |
1.279 + (RM(ir) * RN(ir));
1.280 + break;
1.281 + case 8:
1.282 + switch( (ir&0x0FF0)>>4 ) {
1.283 + case 0: /* CLRT */
1.284 + sh4r.t = 0;
1.285 + break;
1.286 + case 1: /* SETT */
1.287 + sh4r.t = 1;
1.288 + break;
1.289 + case 2: /* CLRMAC */
1.290 + sh4r.mac = 0;
1.291 + break;
1.292 + case 3: /* LDTLB */
1.293 + break;
1.294 + case 4: /* CLRS */
1.295 + sh4r.s = 0;
1.296 + break;
1.297 + case 5: /* SETS */
1.298 + sh4r.s = 1;
1.299 + break;
1.300 + default: UNDEF(ir);
1.301 + }
1.302 + break;
1.303 + case 9:
1.304 + if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
1.305 + RN(ir) = sh4r.t;
1.306 + else if( ir == 0x0019 ) /* DIV0U */
1.307 + sh4r.m = sh4r.q = sh4r.t = 0;
1.308 + else if( ir == 0x0009 )
1.309 + /* NOP */;
1.310 + else UNDEF(ir);
1.311 + break;
1.312 + case 10:
1.313 + switch( (ir&0x00F0) >> 4 ) {
1.314 + case 0: /* STS MACH, Rn */
1.315 + RN(ir) = sh4r.mac >> 32;
1.316 + break;
1.317 + case 1: /* STS MACL, Rn */
1.318 + RN(ir) = (uint32_t)sh4r.mac;
1.319 + break;
1.320 + case 2: /* STS PR, Rn */
1.321 + RN(ir) = sh4r.pr;
1.322 + break;
1.323 + case 3: /* STC SGR, Rn */
1.324 + CHECKPRIV();
1.325 + RN(ir) = sh4r.sgr;
1.326 + break;
1.327 + case 5:/* STS FPUL, Rn */
1.328 + RN(ir) = sh4r.fpul;
1.329 + break;
1.330 + case 6: /* STS FPSCR, Rn */
1.331 + RN(ir) = sh4r.fpscr;
1.332 + break;
1.333 + case 15:/* STC DBR, Rn */
1.334 + CHECKPRIV();
1.335 + RN(ir) = sh4r.dbr;
1.336 + break;
1.337 + default: UNDEF(ir);
1.338 + }
1.339 + break;
1.340 + case 11:
1.341 + switch( (ir&0x0FF0)>>4 ) {
1.342 + case 0: /* RTS */
1.343 + CHECKDEST( sh4r.pr );
1.344 + sh4r.pc = sh4r.new_pc;
1.345 + sh4r.new_pc = sh4r.pr;
1.346 + return;
1.347 + case 1: /* SLEEP */
1.348 + running = 0;
1.349 + break;
1.350 + case 2: /* RTE */
1.351 + CHECKPRIV();
1.352 + CHECKDEST( sh4r.spc );
1.353 + sh4r.pc = sh4r.new_pc;
1.354 + sh4r.new_pc = sh4r.spc;
1.355 + sh4_load_sr( sh4r.ssr );
1.356 + return;
1.357 + default:UNDEF(ir);
1.358 + }
1.359 + break;
1.360 + case 12:/* MOV.B [R0+R%d], R%d */
1.361 + RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
1.362 + break;
1.363 + case 13:/* MOV.W [R0+R%d], R%d */
1.364 + RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
1.365 + break;
1.366 + case 14:/* MOV.L [R0+R%d], R%d */
1.367 + RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
1.368 + break;
1.369 + case 15:/* MAC.L [Rm++], [Rn++] */
1.370 + tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
1.371 + SIGNEXT32(MEM_READ_LONG(RN(ir))) );
1.372 + if( sh4r.s ) {
1.373 + /* 48-bit Saturation. Yuch */
1.374 + tmpl += SIGNEXT48(sh4r.mac);
1.375 + if( tmpl < 0xFFFF800000000000 )
1.376 + tmpl = 0xFFFF800000000000;
1.377 + else if( tmpl > 0x00007FFFFFFFFFFF )
1.378 + tmpl = 0x00007FFFFFFFFFFF;
1.379 + sh4r.mac = (sh4r.mac&0xFFFF000000000000) |
1.380 + (tmpl&0x0000FFFFFFFFFFFF);
1.381 + } else sh4r.mac = tmpl;
1.382 +
1.383 + RM(ir) += 4;
1.384 + RN(ir) += 4;
1.385 +
1.386 + break;
1.387 + default: UNDEF(ir);
1.388 + }
1.389 + break;
1.390 + case 1: /* 0001nnnnmmmmdddd */
1.391 + /* MOV.L Rm, [Rn + disp4*4] */
1.392 + MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
1.393 + break;
1.394 + case 2: /* 0010nnnnmmmmxxxx */
1.395 + switch( ir&0x000F ) {
1.396 + case 0: /* MOV.B Rm, [Rn] */
1.397 + MEM_WRITE_BYTE( RN(ir), RM(ir) );
1.398 + break;
1.399 + case 1: /* MOV.W Rm, [Rn] */
1.400 + MEM_WRITE_WORD( RN(ir), RM(ir) );
1.401 + break;
1.402 + case 2: /* MOV.L Rm, [Rn] */
1.403 + MEM_WRITE_LONG( RN(ir), RM(ir) );
1.404 + break;
1.405 + case 3: UNDEF(ir);
1.406 + break;
1.407 + case 4: /* MOV.B Rm, [--Rn] */
1.408 + RN(ir) --;
1.409 + MEM_WRITE_BYTE( RN(ir), RM(ir) );
1.410 + break;
1.411 + case 5: /* MOV.W Rm, [--Rn] */
1.412 + RN(ir) -= 2;
1.413 + MEM_WRITE_WORD( RN(ir), RM(ir) );
1.414 + break;
1.415 + case 6: /* MOV.L Rm, [--Rn] */
1.416 + RN(ir) -= 4;
1.417 + MEM_WRITE_LONG( RN(ir), RM(ir) );
1.418 + break;
1.419 + case 7: /* DIV0S Rm, Rn */
1.420 + sh4r.q = RN(ir)>>31;
1.421 + sh4r.m = RM(ir)>>31;
1.422 + sh4r.t = sh4r.q ^ sh4r.m;
1.423 + break;
1.424 + case 8: /* TST Rm, Rn */
1.425 + sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
1.426 + break;
1.427 + case 9: /* AND Rm, Rn */
1.428 + RN(ir) &= RM(ir);
1.429 + break;
1.430 + case 10:/* XOR Rm, Rn */
1.431 + RN(ir) ^= RM(ir);
1.432 + break;
1.433 + case 11:/* OR Rm, Rn */
1.434 + RN(ir) |= RM(ir);
1.435 + break;
1.436 + case 12:/* CMP/STR Rm, Rn */
1.437 + /* set T = 1 if any byte in RM & RN is the same */
1.438 + tmp = RM(ir) ^ RN(ir);
1.439 + sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
1.440 + (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
1.441 + break;
1.442 + case 13:/* XTRCT Rm, Rn */
1.443 + RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
1.444 + break;
1.445 + case 14:/* MULU.W Rm, Rn */
1.446 + sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000) |
1.447 + (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
1.448 + break;
1.449 + case 15:/* MULS.W Rm, Rn */
1.450 + sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000) |
1.451 + (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
1.452 + break;
1.453 + }
1.454 + break;
1.455 + case 3: /* 0011nnnnmmmmxxxx */
1.456 + switch( ir&0x000F ) {
1.457 + case 0: /* CMP/EQ Rm, Rn */
1.458 + sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
1.459 + break;
1.460 + case 2: /* CMP/HS Rm, Rn */
1.461 + sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
1.462 + break;
1.463 + case 3: /* CMP/GE Rm, Rn */
1.464 + sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
1.465 + break;
1.466 + case 4: { /* DIV1 Rm, Rn */
1.467 + /* This is just from the sh4p manual with some
1.468 + * simplifications (someone want to check it's correct? :)
1.469 + * Why they couldn't just provide a real DIV instruction...
1.470 + * Please oh please let the translator batch these things
1.471 + * up into a single DIV... */
1.472 + uint32_t tmp0, tmp1, tmp2, dir;
1.473 +
1.474 + dir = sh4r.q ^ sh4r.m;
1.475 + sh4r.q = (RN(ir) >> 31);
1.476 + tmp2 = RM(ir);
1.477 + RN(ir) = (RN(ir) << 1) | sh4r.t;
1.478 + tmp0 = RN(ir);
1.479 + if( dir ) {
1.480 + RN(ir) += tmp2;
1.481 + tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
1.482 + } else {
1.483 + RN(ir) -= tmp2;
1.484 + tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
1.485 + }
1.486 + sh4r.q ^= sh4r.m ^ tmp1;
1.487 + sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
1.488 + break; }
1.489 + case 5: /* DMULU.L Rm, Rn */
1.490 + sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
1.491 + break;
1.492 + case 6: /* CMP/HI Rm, Rn */
1.493 + sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
1.494 + break;
1.495 + case 7: /* CMP/GT Rm, Rn */
1.496 + sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
1.497 + break;
1.498 + case 8: /* SUB Rm, Rn */
1.499 + RN(ir) -= RM(ir);
1.500 + break;
1.501 + case 10:/* SUBC Rm, Rn */
1.502 + tmp = RN(ir);
1.503 + RN(ir) = RN(ir) - RM(ir) - sh4r.t;
1.504 + sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
1.505 + break;
1.506 + case 11:/* SUBV Rm, Rn */
1.507 + UNIMP(ir);
1.508 + break;
1.509 + case 12:/* ADD Rm, Rn */
1.510 + RN(ir) += RM(ir);
1.511 + break;
1.512 + case 13:/* DMULS.L Rm, Rn */
1.513 + sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
1.514 + break;
1.515 + case 14:/* ADDC Rm, Rn */
1.516 + tmp = RN(ir);
1.517 + RN(ir) += RM(ir) + sh4r.t;
1.518 + sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
1.519 + break;
1.520 + case 15:/* ADDV Rm, Rn */
1.521 + UNIMP(ir);
1.522 + break;
1.523 + default: UNDEF(ir);
1.524 + }
1.525 + break;
1.526 + case 4: /* 0100nnnnxxxxxxxx */
1.527 + switch( ir&0x00FF ) {
1.528 + case 0x00: /* SHLL Rn */
1.529 + sh4r.t = RN(ir) >> 31;
1.530 + RN(ir) <<= 1;
1.531 + break;
1.532 + case 0x01: /* SHLR Rn */
1.533 + sh4r.t = RN(ir) & 0x00000001;
1.534 + RN(ir) >>= 1;
1.535 + break;
1.536 + case 0x02: /* STS.L MACH, [--Rn] */
1.537 + RN(ir) -= 4;
1.538 + MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
1.539 + break;
1.540 + case 0x03: /* STC.L SR, [--Rn] */
1.541 + CHECKPRIV();
1.542 + RN(ir) -= 4;
1.543 + MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
1.544 + break;
1.545 + case 0x04: /* ROTL Rn */
1.546 + sh4r.t = RN(ir) >> 31;
1.547 + RN(ir) <<= 1;
1.548 + RN(ir) |= sh4r.t;
1.549 + break;
1.550 + case 0x05: /* ROTR Rn */
1.551 + sh4r.t = RN(ir) & 0x00000001;
1.552 + RN(ir) >>= 1;
1.553 + RN(ir) |= (sh4r.t << 31);
1.554 + break;
1.555 + case 0x06: /* LDS.L [Rn++], MACH */
1.556 + sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1.557 + (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
1.558 + RN(ir) += 4;
1.559 + break;
1.560 + case 0x07: /* LDC.L [Rn++], SR */
1.561 + CHECKPRIV();
1.562 + sh4_load_sr( MEM_READ_LONG(RN(ir)) );
1.563 + RN(ir) +=4;
1.564 + break;
1.565 + case 0x08: /* SHLL2 Rn */
1.566 + RN(ir) <<= 2;
1.567 + break;
1.568 + case 0x09: /* SHLR2 Rn */
1.569 + RN(ir) >>= 2;
1.570 + break;
1.571 + case 0x0A: /* LDS Rn, MACH */
1.572 + sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1.573 + (((uint64_t)RN(ir))<<32);
1.574 + break;
1.575 + case 0x0B: /* JSR [Rn] */
1.576 + CHECKDEST( RN(ir) );
1.577 + sh4r.pc = sh4r.new_pc;
1.578 + sh4r.new_pc = RN(ir);
1.579 + sh4r.pr = pc + 4;
1.580 + return;
1.581 + case 0x0E: /* LDC Rn, SR */
1.582 + CHECKPRIV();
1.583 + sh4_load_sr( RN(ir) );
1.584 + break;
1.585 + case 0x10: /* DT Rn */
1.586 + RN(ir) --;
1.587 + sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
1.588 + break;
1.589 + case 0x11: /* CMP/PZ Rn */
1.590 + sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
1.591 + break;
1.592 + case 0x12: /* STS.L MACL, [--Rn] */
1.593 + RN(ir) -= 4;
1.594 + MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
1.595 + break;
1.596 + case 0x13: /* STC.L GBR, [--Rn] */
1.597 + RN(ir) -= 4;
1.598 + MEM_WRITE_LONG( RN(ir), sh4r.gbr );
1.599 + break;
1.600 + case 0x15: /* CMP/PL Rn */
1.601 + sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
1.602 + break;
1.603 + case 0x16: /* LDS.L [Rn++], MACL */
1.604 + sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000) |
1.605 + (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
1.606 + RN(ir) += 4;
1.607 + break;
1.608 + case 0x17: /* LDC.L [Rn++], GBR */
1.609 + sh4r.gbr = MEM_READ_LONG(RN(ir));
1.610 + RN(ir) +=4;
1.611 + break;
1.612 + case 0x18: /* SHLL8 Rn */
1.613 + RN(ir) <<= 8;
1.614 + break;
1.615 + case 0x19: /* SHLR8 Rn */
1.616 + RN(ir) >>= 8;
1.617 + break;
1.618 + case 0x1A: /* LDS Rn, MACL */
1.619 + sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000) |
1.620 + (uint64_t)((uint32_t)(RN(ir)));
1.621 + break;
1.622 + case 0x1B: /* TAS.B [Rn] */
1.623 + tmp = MEM_READ_BYTE( RN(ir) );
1.624 + sh4r.t = ( tmp == 0 ? 1 : 0 );
1.625 + MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
1.626 + break;
1.627 + case 0x1E: /* LDC Rn, GBR */
1.628 + sh4r.gbr = RN(ir);
1.629 + break;
1.630 + case 0x20: /* SHAL Rn */
1.631 + sh4r.t = RN(ir) >> 31;
1.632 + RN(ir) <<= 1;
1.633 + break;
1.634 + case 0x21: /* SHAR Rn */
1.635 + sh4r.t = RN(ir) & 0x00000001;
1.636 + RN(ir) = ((int32_t)RN(ir)) >> 1;
1.637 + break;
1.638 + case 0x22: /* STS.L PR, [--Rn] */
1.639 + RN(ir) -= 4;
1.640 + MEM_WRITE_LONG( RN(ir), sh4r.pr );
1.641 + break;
1.642 + case 0x23: /* STC.L VBR, [--Rn] */
1.643 + CHECKPRIV();
1.644 + RN(ir) -= 4;
1.645 + MEM_WRITE_LONG( RN(ir), sh4r.pr );
1.646 + break;
1.647 + case 0x24: /* ROTCL Rn */
1.648 + tmp = RN(ir) >> 31;
1.649 + RN(ir) <<= 1;
1.650 + RN(ir) |= sh4r.t;
1.651 + sh4r.t = tmp;
1.652 + break;
1.653 + case 0x25: /* ROTCR Rn */
1.654 + tmp = RN(ir) & 0x00000001;
1.655 + RN(ir) >>= 1;
1.656 + RN(ir) |= (sh4r.t << 31 );
1.657 + sh4r.t = tmp;
1.658 + break;
1.659 + case 0x26: /* LDS.L [Rn++], PR */
1.660 + sh4r.pr = MEM_READ_LONG( RN(ir) );
1.661 + RN(ir) += 4;
1.662 + break;
1.663 + case 0x27: /* LDC.L [Rn++], VBR */
1.664 + CHECKPRIV();
1.665 + sh4r.vbr = MEM_READ_LONG(RN(ir));
1.666 + RN(ir) +=4;
1.667 + break;
1.668 + case 0x28: /* SHLL16 Rn */
1.669 + RN(ir) <<= 16;
1.670 + break;
1.671 + case 0x29: /* SHLR16 Rn */
1.672 + RN(ir) >>= 16;
1.673 + break;
1.674 + case 0x2A: /* LDS Rn, PR */
1.675 + sh4r.pr = RN(ir);
1.676 + break;
1.677 + case 0x2B: /* JMP [Rn] */
1.678 + CHECKDEST( RN(ir) );
1.679 + sh4r.pc = sh4r.new_pc;
1.680 + sh4r.new_pc = RN(ir);
1.681 + return;
1.682 + case 0x2E: /* LDC Rn, VBR */
1.683 + CHECKPRIV();
1.684 + sh4r.vbr = RN(ir);
1.685 + break;
1.686 + case 0x32: /* STC.L SGR, [--Rn] */
1.687 + CHECKPRIV();
1.688 + RN(ir) -= 4;
1.689 + MEM_WRITE_LONG( RN(ir), sh4r.sgr );
1.690 + break;
1.691 + case 0x33: /* STC.L SSR, [--Rn] */
1.692 + CHECKPRIV();
1.693 + RN(ir) -= 4;
1.694 + MEM_WRITE_LONG( RN(ir), sh4r.ssr );
1.695 + break;
1.696 + case 0x37: /* LDC.L [Rn++], SSR */
1.697 + CHECKPRIV();
1.698 + sh4r.ssr = MEM_READ_LONG(RN(ir));
1.699 + RN(ir) +=4;
1.700 + break;
1.701 + case 0x3E: /* LDC Rn, SSR */
1.702 + CHECKPRIV();
1.703 + sh4r.ssr = RN(ir);
1.704 + break;
1.705 + case 0x43: /* STC.L SPC, [--Rn] */
1.706 + CHECKPRIV();
1.707 + RN(ir) -= 4;
1.708 + MEM_WRITE_LONG( RN(ir), sh4r.spc );
1.709 + break;
1.710 + case 0x47: /* LDC.L [Rn++], SPC */
1.711 + CHECKPRIV();
1.712 + sh4r.spc = MEM_READ_LONG(RN(ir));
1.713 + RN(ir) +=4;
1.714 + break;
1.715 + case 0x4E: /* LDC Rn, SPC */
1.716 + CHECKPRIV();
1.717 + sh4r.spc = RN(ir);
1.718 + break;
1.719 + case 0x52: /* STS.L FPUL, [--Rn] */
1.720 + RN(ir) -= 4;
1.721 + MEM_WRITE_LONG( RN(ir), sh4r.fpul );
1.722 + break;
1.723 + case 0x56: /* LDS.L [Rn++], FPUL */
1.724 + sh4r.fpul = MEM_READ_LONG(RN(ir));
1.725 + RN(ir) +=4;
1.726 + break;
1.727 + case 0x5A: /* LDS Rn, FPUL */
1.728 + sh4r.fpul = RN(ir);
1.729 + break;
1.730 + case 0x62: /* STS.L FPSCR, [--Rn] */
1.731 + RN(ir) -= 4;
1.732 + MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
1.733 + break;
1.734 + case 0x66: /* LDS.L [Rn++], FPSCR */
1.735 + sh4r.fpscr = MEM_READ_LONG(RN(ir));
1.736 + RN(ir) +=4;
1.737 + break;
1.738 + case 0x6A: /* LDS Rn, FPSCR */
1.739 + sh4r.fpscr = RN(ir);
1.740 + break;
1.741 + case 0xF2: /* STC.L DBR, [--Rn] */
1.742 + CHECKPRIV();
1.743 + RN(ir) -= 4;
1.744 + MEM_WRITE_LONG( RN(ir), sh4r.dbr );
1.745 + break;
1.746 + case 0xF6: /* LDC.L [Rn++], DBR */
1.747 + CHECKPRIV();
1.748 + sh4r.dbr = MEM_READ_LONG(RN(ir));
1.749 + RN(ir) +=4;
1.750 + break;
1.751 + case 0xFA: /* LDC Rn, DBR */
1.752 + CHECKPRIV();
1.753 + sh4r.dbr = RN(ir);
1.754 + break;
1.755 + case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
1.756 + case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
1.757 + CHECKPRIV();
1.758 + RN(ir) -= 4;
1.759 + MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
1.760 + break;
1.761 + case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
1.762 + case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
1.763 + CHECKPRIV();
1.764 + RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
1.765 + RN(ir) += 4;
1.766 + break;
1.767 + case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
1.768 + case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
1.769 + CHECKPRIV();
1.770 + RN_BANK(ir) = RM(ir);
1.771 + break;
1.772 + default:
1.773 + if( (ir&0x000F) == 0x0F ) {
1.774 + /* MAC.W [Rm++], [Rn++] */
1.775 + tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
1.776 + SIGNEXT16(MEM_READ_WORD(RN(ir)));
1.777 + if( sh4r.s ) {
1.778 + /* FIXME */
1.779 + UNIMP(ir);
1.780 + } else sh4r.mac += SIGNEXT32(tmp);
1.781 + RM(ir) += 2;
1.782 + RN(ir) += 2;
1.783 + } else if( (ir&0x000F) == 0x0C ) {
1.784 + /* SHAD Rm, Rn */
1.785 + tmp = RM(ir);
1.786 + if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1.787 + else if( (tmp & 0x1F) == 0 ) ((int32_t)RN(ir)) >>=31;
1.788 + else ((int32_t)RN(ir)) >>= (((~RM(ir)) & 0x1F)+1);
1.789 + } else if( (ir&0x000F) == 0x0D ) {
1.790 + /* SHLD Rm, Rn */
1.791 + tmp = RM(ir);
1.792 + if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1.793 + else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
1.794 + else RN(ir) >>= (((~tmp) & 0x1F)+1);
1.795 + } else UNDEF(ir);
1.796 + }
1.797 + break;
1.798 + case 5: /* 0101nnnnmmmmdddd */
1.799 + /* MOV.L [Rm + disp4*4], Rn */
1.800 + RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
1.801 + break;
1.802 + case 6: /* 0110xxxxxxxxxxxx */
1.803 + switch( ir&0x000f ) {
1.804 + case 0: /* MOV.B [Rm], Rn */
1.805 + RN(ir) = MEM_READ_BYTE( RM(ir) );
1.806 + break;
1.807 + case 1: /* MOV.W [Rm], Rn */
1.808 + RN(ir) = MEM_READ_WORD( RM(ir) );
1.809 + break;
1.810 + case 2: /* MOV.L [Rm], Rn */
1.811 + RN(ir) = MEM_READ_LONG( RM(ir) );
1.812 + break;
1.813 + case 3: /* MOV Rm, Rn */
1.814 + RN(ir) = RM(ir);
1.815 + break;
1.816 + case 4: /* MOV.B [Rm++], Rn */
1.817 + RN(ir) = MEM_READ_BYTE( RM(ir) );
1.818 + RM(ir) ++;
1.819 + break;
1.820 + case 5: /* MOV.W [Rm++], Rn */
1.821 + RN(ir) = MEM_READ_WORD( RM(ir) );
1.822 + RM(ir) += 2;
1.823 + break;
1.824 + case 6: /* MOV.L [Rm++], Rn */
1.825 + RN(ir) = MEM_READ_LONG( RM(ir) );
1.826 + RM(ir) += 4;
1.827 + break;
1.828 + case 7: /* NOT Rm, Rn */
1.829 + RN(ir) = ~RM(ir);
1.830 + break;
1.831 + case 8: /* SWAP.B Rm, Rn */
1.832 + RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
1.833 + ((RM(ir)&0x000000FF)<<8);
1.834 + break;
1.835 + case 9: /* SWAP.W Rm, Rn */
1.836 + RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
1.837 + break;
1.838 + case 10:/* NEGC Rm, Rn */
1.839 + tmp = 0 - RM(ir);
1.840 + RN(ir) = tmp - sh4r.t;
1.841 + sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
1.842 + break;
1.843 + case 11:/* NEG Rm, Rn */
1.844 + RN(ir) = 0 - RM(ir);
1.845 + break;
1.846 + case 12:/* EXTU.B Rm, Rn */
1.847 + RN(ir) = RM(ir)&0x000000FF;
1.848 + break;
1.849 + case 13:/* EXTU.W Rm, Rn */
1.850 + RN(ir) = RM(ir)&0x0000FFFF;
1.851 + break;
1.852 + case 14:/* EXTS.B Rm, Rn */
1.853 + RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
1.854 + break;
1.855 + case 15:/* EXTS.W Rm, Rn */
1.856 + RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
1.857 + break;
1.858 + }
1.859 + break;
1.860 + case 7: /* 0111nnnniiiiiiii */
1.861 + /* ADD imm8, Rn */
1.862 + RN(ir) += IMM8(ir);
1.863 + break;
1.864 + case 8: /* 1000xxxxxxxxxxxx */
1.865 + switch( (ir&0x0F00) >> 8 ) {
1.866 + case 0: /* MOV.B R0, [Rm + disp4] */
1.867 + MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
1.868 + break;
1.869 + case 1: /* MOV.W R0, [Rm + disp4*2] */
1.870 + MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
1.871 + break;
1.872 + case 4: /* MOV.B [Rm + disp4], R0 */
1.873 + R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
1.874 + break;
1.875 + case 5: /* MOV.W [Rm + disp4*2], R0 */
1.876 + R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
1.877 + break;
1.878 + case 8: /* CMP/EQ imm, R0 */
1.879 + sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
1.880 + break;
1.881 + case 9: /* BT disp8 */
1.882 + if( sh4r.t ) {
1.883 + CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1.884 + sh4r.pc += (PCDISP8(ir)<<1) + 4;
1.885 + sh4r.new_pc = sh4r.pc + 2;
1.886 + return;
1.887 + }
1.888 + break;
1.889 + case 11:/* BF disp8 */
1.890 + if( !sh4r.t ) {
1.891 + CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1.892 + sh4r.pc += (PCDISP8(ir)<<1) + 4;
1.893 + sh4r.new_pc = sh4r.pc + 2;
1.894 + return;
1.895 + }
1.896 + break;
1.897 + case 13:/* BT/S disp8 */
1.898 + if( sh4r.t ) {
1.899 + CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1.900 + sh4r.pc = sh4r.new_pc;
1.901 + sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1.902 + return;
1.903 + }
1.904 + break;
1.905 + case 15:/* BF/S disp8 */
1.906 + if( !sh4r.t ) {
1.907 + CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1.908 + sh4r.pc = sh4r.new_pc;
1.909 + sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1.910 + return;
1.911 + }
1.912 + break;
1.913 + default: UNDEF(ir);
1.914 + }
1.915 + break;
1.916 + case 9: /* 1001xxxxxxxxxxxx */
1.917 + /* MOV.W [disp8*2 + pc + 4], Rn */
1.918 + RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
1.919 + break;
1.920 + case 10:/* 1010dddddddddddd */
1.921 + /* BRA disp12 */
1.922 + CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 );
1.923 + sh4r.pc = sh4r.new_pc;
1.924 + sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1.925 + return;
1.926 + case 11:/* 1011dddddddddddd */
1.927 + /* BSR disp12 */
1.928 + CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1.929 + sh4r.pr = pc + 4;
1.930 + sh4r.pc = sh4r.new_pc;
1.931 + sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1.932 + return;
1.933 + case 12:/* 1100xxxxdddddddd */
1.934 + switch( (ir&0x0F00)>>8 ) {
1.935 + case 0: /* MOV.B R0, [GBR + disp8] */
1.936 + MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1.937 + break;
1.938 + case 1: /* MOV.W R0, [GBR + disp8*2] */
1.939 + MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
1.940 + break;
1.941 + case 2: /*MOV.L R0, [GBR + disp8*4] */
1.942 + MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
1.943 + break;
1.944 + case 3: /* TRAPA imm8 */
1.945 + MMIO_WRITE( MMU, TRA, UIMM8(ir) );
1.946 + sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */
1.947 + sh4r.new_pc += 2;
1.948 + RAISE( EXC_TRAP, EXV_TRAP );
1.949 + break;
1.950 + case 4: /* MOV.B [GBR + disp8], R0 */
1.951 + R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1.952 + break;
1.953 + case 5: /* MOV.W [GBR + disp8*2], R0 */
1.954 + R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
1.955 + break;
1.956 + case 6: /* MOV.L [GBR + disp8*4], R0 */
1.957 + R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
1.958 + break;
1.959 + case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1.960 + R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1.961 + break;
1.962 + case 8: /* TST imm8, R0 */
1.963 + sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1.964 + break;
1.965 + case 9: /* AND imm8, R0 */
1.966 + R0 &= UIMM8(ir);
1.967 + break;
1.968 + case 10:/* XOR imm8, R0 */
1.969 + R0 ^= UIMM8(ir);
1.970 + break;
1.971 + case 11:/* OR imm8, R0 */
1.972 + R0 |= UIMM8(ir);
1.973 + break;
1.974 + case 12:/* TST.B imm8, [R0+GBR] */
1.975 + sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1.976 + break;
1.977 + case 13:/* AND.B imm8, [R0+GBR] */
1.978 + MEM_WRITE_BYTE( R0 + sh4r.gbr,
1.979 + UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1.980 + break;
1.981 + case 14:/* XOR.B imm8, [R0+GBR] */
1.982 + MEM_WRITE_BYTE( R0 + sh4r.gbr,
1.983 + UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1.984 + break;
1.985 + case 15:/* OR.B imm8, [R0+GBR] */
1.986 + MEM_WRITE_BYTE( R0 + sh4r.gbr,
1.987 + UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1.988 + break;
1.989 + }
1.990 + break;
1.991 + case 13:/* 1101nnnndddddddd */
1.992 + /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1.993 + RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
1.994 + break;
1.995 + case 14:/* 1110nnnniiiiiiii */
1.996 + /* MOV imm8, Rn */
1.997 + RN(ir) = IMM8(ir);
1.998 + break;
1.999 + case 15:/* 1111xxxxxxxxxxxx */
1.1000 + CHECKFPUEN();
1.1001 + switch( ir&0x000F ) {
1.1002 + case 0: /* FADD FRm, FRn */
1.1003 + FRN(ir) += FRM(ir);
1.1004 + break;
1.1005 + case 1: /* FSUB FRm, FRn */
1.1006 + FRN(ir) -= FRM(ir);
1.1007 + break;
1.1008 + case 2: /* FMUL FRm, FRn */
1.1009 + FRN(ir) = FRN(ir) * FRM(ir);
1.1010 + break;
1.1011 + case 3: /* FDIV FRm, FRn */
1.1012 + FRN(ir) = FRN(ir) / FRM(ir);
1.1013 + break;
1.1014 + case 4: /* FCMP/EQ FRm, FRn */
1.1015 + sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1.1016 + break;
1.1017 + case 5: /* FCMP/GT FRm, FRn */
1.1018 + sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1.1019 + break;
1.1020 + case 6: /* FMOV.S [Rm+R0], FRn */
1.1021 + MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1.1022 + break;
1.1023 + case 7: /* FMOV.S FRm, [Rn+R0] */
1.1024 + MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1.1025 + break;
1.1026 + case 8: /* FMOV.S [Rm], FRn */
1.1027 + MEM_FP_READ( RM(ir), FRNn(ir) );
1.1028 + break;
1.1029 + case 9: /* FMOV.S [Rm++], FRn */
1.1030 + MEM_FP_READ( RM(ir), FRNn(ir) );
1.1031 + RM(ir) += FP_WIDTH;
1.1032 + break;
1.1033 + case 10:/* FMOV.S FRm, [Rn] */
1.1034 + MEM_FP_WRITE( RN(ir), FRMn(ir) );
1.1035 + break;
1.1036 + case 11:/* FMOV.S FRm, [--Rn] */
1.1037 + RN(ir) -= FP_WIDTH;
1.1038 + MEM_FP_WRITE( RN(ir), FRMn(ir) );
1.1039 + break;
1.1040 + case 12:/* FMOV FRm, FRn */
1.1041 + if( IS_FPU_DOUBLESIZE() ) {
1.1042 + DRN(ir) = DRM(ir);
1.1043 + } else {
1.1044 + FRN(ir) = FRM(ir);
1.1045 + }
1.1046 + break;
1.1047 + case 13:
1.1048 + switch( (ir&0x00F0) >> 4 ) {
1.1049 + case 0: /* FSTS FPUL, FRn */
1.1050 + FRN(ir) = FPULf;
1.1051 + break;
1.1052 + case 1: /* FLDS FRn, FPUL */
1.1053 + FPULf = FRN(ir);
1.1054 + break;
1.1055 + case 2: /* FLOAT FPUL, FRn */
1.1056 + FRN(ir) = (float)FPULi;
1.1057 + break;
1.1058 + case 3: /* FTRC FRn, FPUL */
1.1059 + FPULi = (uint32_t)FRN(ir);
1.1060 + /* FIXME: is this sufficient? */
1.1061 + break;
1.1062 + case 4: /* FNEG FRn */
1.1063 + FRN(ir) = -FRN(ir);
1.1064 + break;
1.1065 + case 5: /* FABS FRn */
1.1066 + FRN(ir) = fabsf(FRN(ir));
1.1067 + break;
1.1068 + case 6: /* FSQRT FRn */
1.1069 + FRN(ir) = sqrtf(FRN(ir));
1.1070 + break;
1.1071 + case 8: /* FLDI0 FRn */
1.1072 + FRN(ir) = 0.0;
1.1073 + break;
1.1074 + case 9: /* FLDI1 FRn */
1.1075 + FRN(ir) = 1.0;
1.1076 + break;
1.1077 + case 10: /* FCNVSD FPUL, DRn */
1.1078 + if( IS_FPU_DOUBLEPREC() )
1.1079 + DRN(ir) = (double)FPULf;
1.1080 + else UNDEF(ir);
1.1081 + break;
1.1082 + case 11: /* FCNVDS DRn, FPUL */
1.1083 + if( IS_FPU_DOUBLEPREC() )
1.1084 + FPULf = (float)DRN(ir);
1.1085 + else UNDEF(ir);
1.1086 + break;
1.1087 + case 14:/* FIPR FVn, FVn */
1.1088 + UNIMP(ir);
1.1089 + break;
1.1090 + case 15:
1.1091 + if( FVM(ir) == 1 )
1.1092 + /* FTRV XMTRX,FVn */
1.1093 + UNIMP(ir);
1.1094 + else if( ir == 0xFBFD )
1.1095 + /* FRCHG */
1.1096 + sh4r.fpscr ^= FPSCR_FR;
1.1097 + else if( ir == 0xF3FD )
1.1098 + sh4r.fpscr ^= FPSCR_SZ;
1.1099 + /* FSCHG */
1.1100 + break;
1.1101 + default: UNDEF(ir);
1.1102 + }
1.1103 + break;
1.1104 + case 14:/* FMAC FR0, FRm, FRn */
1.1105 + FRN(ir) += FRM(ir)*FR0;
1.1106 + break;
1.1107 + default: UNDEF(ir);
1.1108 + }
1.1109 + break;
1.1110 + }
1.1111 + sh4r.pc = sh4r.new_pc;
1.1112 + sh4r.new_pc += 2;
1.1113 +}
.