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lxdream.org :: lxdream/src/sh4/sh4core.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.h
changeset 1:eea311cfd33e
next2:42349f6ea216
author nkeynes
date Sat Mar 13 00:03:32 2004 +0000 (16 years ago)
permissions -rw-r--r--
last change This commit was generated by cvs2svn to compensate for changes in r2,
which included commits to RCS files with non-trunk default branches.
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/sh4/sh4core.h Sat Mar 13 00:03:32 2004 +0000
1.3 @@ -0,0 +1,108 @@
1.4 +/*
1.5 + * Header for the basic sh4 emulator core
1.6 + */
1.7 +#ifndef sh4core_H
1.8 +#define sh4core_H 1
1.9 +
1.10 +#include <stdint.h>
1.11 +
1.12 +#ifdef __cplusplus
1.13 +extern "C" {
1.14 +#if 0
1.15 +}
1.16 +#endif
1.17 +#endif
1.18 +
1.19 +struct sh4_registers {
1.20 + uint32_t r[16];
1.21 + uint32_t r_bank[8]; /* hidden banked registers */
1.22 + uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
1.23 + uint32_t pr, pc, fpul, fpscr;
1.24 + uint64_t mac;
1.25 + uint32_t m, q, s, t; /* really boolean - 0 or 1 */
1.26 + float fr[2][16];
1.27 +
1.28 + uint32_t new_pc; /* Not a real register, but used to handle delay slots */
1.29 + uint32_t icount; /* Also not a real register, instruction counter */
1.30 + uint32_t int_pending; /* flag set by the INTC = pending priority level */
1.31 +};
1.32 +
1.33 +extern struct sh4_registers sh4r;
1.34 +
1.35 +/* Public functions */
1.36 +
1.37 +void sh4_init( void );
1.38 +void sh4_reset( void );
1.39 +void sh4_run( void );
1.40 +void sh4_runto( uint32_t pc, uint32_t count );
1.41 +void sh4_runfor( uint32_t count );
1.42 +int sh4_isrunning( void );
1.43 +void sh4_stop( void );
1.44 +void sh4_set_pc( int );
1.45 +void sh4_execute_instruction( void );
1.46 +void sh4_raise_exception( int, int );
1.47 +
1.48 +void run_timers( int );
1.49 +
1.50 +#define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
1.51 +#define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
1.52 +#define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
1.53 +#define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
1.54 +#define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
1.55 +#define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
1.56 +
1.57 +/* Status Register (SR) bits */
1.58 +#define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
1.59 +#define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
1.60 +#define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
1.61 +#define SR_FD 0x00008000 /* FPU disable */
1.62 +#define SR_M 0x00000200
1.63 +#define SR_Q 0x00000100
1.64 +#define SR_IMASK 0x000000F0 /* Interrupt mask level */
1.65 +#define SR_S 0x00000002 /* Saturation operation for MAC instructions */
1.66 +#define SR_T 0x00000001 /* True/false or carry/borrow */
1.67 +#define SR_MASK 0x700083F3
1.68 +#define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
1.69 +
1.70 +#define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
1.71 +#define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
1.72 +#define SH4_INT_PENDING() (sh4r.int_pending)
1.73 +
1.74 +#define FPSCR_FR 0x00200000 /* FPU register bank */
1.75 +#define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
1.76 +#define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
1.77 +#define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
1.78 +#define FPSCR_CAUSE 0x0003F000
1.79 +#define FPSCR_ENABLE 0x00000F80
1.80 +#define FPSCR_FLAG 0x0000007C
1.81 +#define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
1.82 +
1.83 +#define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
1.84 +#define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
1.85 +#define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
1.86 +
1.87 +#define FR sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]
1.88 +
1.89 +/* Exceptions (for use with sh4_raise_exception) */
1.90 +
1.91 +#define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
1.92 +#define EX_SLOT_ILLEGAL 0x1A0, 0x100
1.93 +#define EX_TLB_MISS_READ 0x040, 0x400
1.94 +#define EX_TLB_MISS_WRITE 0x060, 0x400
1.95 +#define EX_INIT_PAGE_WRITE 0x080, 0x100
1.96 +#define EX_TLB_PROT_READ 0x0A0, 0x100
1.97 +#define EX_TLB_PROT_WRITE 0x0C0, 0x100
1.98 +#define EX_DATA_ADDR_READ 0x0E0, 0x100
1.99 +#define EX_DATA_ADDR_WRITE 0x100, 0x100
1.100 +#define EX_FPU_EXCEPTION 0x120, 0x100
1.101 +#define EX_TRAPA 0x160, 0x100
1.102 +#define EX_BREAKPOINT 0x1E0, 0x100
1.103 +#define EX_FPU_DISABLED 0x800, 0x100
1.104 +#define EX_SLOT_FPU_DISABLED 0x820, 0x100
1.105 +
1.106 +
1.107 +
1.108 +#ifdef __cplusplus
1.109 +}
1.110 +#endif
1.111 +#endif
.