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lxdream.org :: lxdream/src/sh4/sh4mmio.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.h
changeset 1:eea311cfd33e
next10:c898b37506e0
author nkeynes
date Sat Mar 13 00:03:32 2004 +0000 (17 years ago)
permissions -rw-r--r--
last change This commit was generated by cvs2svn to compensate for changes in r2,
which included commits to RCS files with non-trunk default branches.
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/sh4/sh4mmio.h Sat Mar 13 00:03:32 2004 +0000
1.3 @@ -0,0 +1,153 @@
1.4 +#include "mmio.h"
1.5 +
1.6 +#if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \
1.7 + (!defined(MMIO_IMPL) && !defined(SH4MMIO_IFACE))
1.8 +
1.9 +#ifdef MMIO_IMPL
1.10 +#define SH4MMIO_IMPL
1.11 +#else
1.12 +#define SH4MMIO_IFACE
1.13 +#endif
1.14 +/* SH7750 onchip mmio devices */
1.15 +
1.16 +MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
1.17 + LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" )
1.18 + LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" )
1.19 + LONG_PORT( 0x008, TTB, PORT_MRW, UNDEFINED, "Translation table base" )
1.20 + LONG_PORT( 0x00C, TEA, PORT_MRW, UNDEFINED, "TLB exception address" )
1.21 + LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" )
1.22 + BYTE_PORT( 0x14, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
1.23 + BYTE_PORT( 0x18, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
1.24 + LONG_PORT( 0x01C, CCR, PORT_MRW, 0, "Cache control register" )
1.25 + LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" )
1.26 + LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
1.27 + LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" )
1.28 + LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
1.29 + LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
1.30 + LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )
1.31 +MMIO_REGION_END
1.32 +
1.33 +/* User Break Controller (Page 717 [757] of sh7750h manual) */
1.34 +MMIO_REGION_BEGIN( 0xFF200000, UBC, "User Break Controller" )
1.35 + LONG_PORT( 0x000, BARA, PORT_MRW, UNDEFINED, "Break address A" )
1.36 + BYTE_PORT( 0x004, BAMRA, PORT_MRW, UNDEFINED, "Break address mask A" )
1.37 + WORD_PORT( 0x008, BBRA, PORT_MRW, 0, "Break bus cycle A" )
1.38 + LONG_PORT( 0x00C, BARB, PORT_MRW, UNDEFINED, "Break address B" )
1.39 + BYTE_PORT( 0x010, BAMRB, PORT_MRW, UNDEFINED, "Break address mask B" )
1.40 + WORD_PORT( 0x014, BBRB, PORT_MRW, 0, "Break bus cycle B" )
1.41 + LONG_PORT( 0x018, BDRB, PORT_MRW, UNDEFINED, "Break data B" )
1.42 + LONG_PORT( 0x01C, BDMRB, PORT_MRW, UNDEFINED, "Break data mask B" )
1.43 + WORD_PORT( 0x020, BRCR, PORT_MRW, 0, "Break control" )
1.44 +MMIO_REGION_END
1.45 +/* Bus State Controller (Page 293 [333] of sh7750h manual)
1.46 + * I/O Ports */
1.47 +MMIO_REGION_BEGIN( 0xFF800000, BSC, "Bus State Controller" )
1.48 + LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "Bus control 1" )
1.49 + WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "Bus control 2" )
1.50 + LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "Wait state control 1" )
1.51 + LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "Wait state control 2" )
1.52 + LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "Wait state control 3" )
1.53 + LONG_PORT( 0x014, MCR, PORT_MRW, 0, "Memory control register" )
1.54 + WORD_PORT( 0x018, PCR, PORT_MRW, 0, "PCMCIA control register" )
1.55 + WORD_PORT( 0x01C, RTCSR, PORT_MRW, 0, "Refresh timer control/status" )
1.56 + WORD_PORT( 0x020, RTCNT, PORT_MRW, 0, "Refresh timer counter" )
1.57 + WORD_PORT( 0x024, RTCOR, PORT_MRW, 0, "Refresh timer constant" )
1.58 + WORD_PORT( 0x028, RFCR, PORT_MRW, 0, "Refresh count" )
1.59 + LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" )
1.60 + WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" )
1.61 + LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" )
1.62 + WORD_PORT( 0x044, PDTRB, PORT_RW, UNDEFINED, "Port data register B" )
1.63 + WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
1.64 +MMIO_REGION_END
1.65 +
1.66 +/* DMA Controller (Page 457 [497] of sh7750h manual) */
1.67 +MMIO_REGION_BEGIN( 0xFFA00000, DMAC, "DMA Controller" )
1.68 + LONG_PORT( 0x000, SAR0, PORT_MRW, UNDEFINED, "DMA source address 0" )
1.69 + LONG_PORT( 0x004, DAR0, PORT_MRW, UNDEFINED, "DMA destination address 0" )
1.70 + LONG_PORT( 0x008, DMATCR0, PORT_MRW, UNDEFINED, "DMA transfer count 0" )
1.71 + LONG_PORT( 0x00C, CHCR0, PORT_MRW, 0, "DMA channel control 0" )
1.72 + LONG_PORT( 0x010, SAR1, PORT_MRW, UNDEFINED, "DMA source address 1" )
1.73 + LONG_PORT( 0x014, DAR1, PORT_MRW, UNDEFINED, "DMA destination address 1" )
1.74 + LONG_PORT( 0x018, DMATCR1, PORT_MRW, UNDEFINED, "DMA transfer count 1" )
1.75 + LONG_PORT( 0x01C, CHCR1, PORT_MRW, 0, "DMA channel control 1" )
1.76 + LONG_PORT( 0x020, SAR2, PORT_MRW, UNDEFINED, "DMA source address 2" )
1.77 + LONG_PORT( 0x024, DAR2, PORT_MRW, UNDEFINED, "DMA destination address 2" )
1.78 + LONG_PORT( 0x028, DMATCR2, PORT_MRW, UNDEFINED, "DMA transfer count 2" )
1.79 + LONG_PORT( 0x02C, CHCR2, PORT_MRW, 0, "DMA channel control 2" )
1.80 + LONG_PORT( 0x030, SAR3, PORT_MRW, UNDEFINED, "DMA source address 3" )
1.81 + LONG_PORT( 0x034, DAR3, PORT_MRW, UNDEFINED, "DMA destination address 3" )
1.82 + LONG_PORT( 0x038, DMATCR3, PORT_MRW, UNDEFINED, "DMA transfer count 3" )
1.83 + LONG_PORT( 0x03C, CHCR3, PORT_MRW, 0, "DMA channel control 3" )
1.84 + LONG_PORT( 0x040, DMAOR, PORT_MRW, 0, "DMA operation register" )
1.85 +MMIO_REGION_END
1.86 +
1.87 +/* Clock Pulse Generator (page 233 [273] of sh7750h manual) */
1.88 +MMIO_REGION_BEGIN( 0xFFC00000, CPG, "Clock Pulse Generator" )
1.89 + WORD_PORT( 0x000, FRQCR, PORT_MRW, UNDEFINED, "Frequency control" )
1.90 + BYTE_PORT( 0x004, STBCR, PORT_MRW, 0, "Standby control" )
1.91 + BYTE_PORT( 0x008, WTCNT, PORT_MRW, 0, "Watchdog timer counter" )
1.92 + BYTE_PORT( 0x00C, WTCSR, PORT_MRW, 0, "Watchdog timer control/status" )
1.93 + BYTE_PORT( 0x010, STBCR2, PORT_MRW, 0, "Standby control 2" )
1.94 +MMIO_REGION_END
1.95 +
1.96 +/* Real time clock (Page 253 [293] of sh7750h manual) */
1.97 +MMIO_REGION_BEGIN( 0xFFC80000, RTC, "Realtime Clock" )
1.98 + BYTE_PORT( 0x000, R64CNT, PORT_R, UNDEFINED, "64 Hz counter" )
1.99 + BYTE_PORT( 0x004, RSECCNT, PORT_MRW, UNDEFINED, "Second counter" )
1.100 + /* ... */
1.101 +MMIO_REGION_END
1.102 +
1.103 +/* Interrupt controller (Page 699 [739] of sh7750h manual) */
1.104 +MMIO_REGION_BEGIN( 0xFFD00000, INTC, "Interrupt Controller" )
1.105 + WORD_PORT( 0x000, ICR, PORT_MRW, 0x0000, "Interrupt control register" )
1.106 + WORD_PORT( 0x004, IPRA, PORT_MRW, 0x0000, "Interrupt priority register A" )
1.107 + WORD_PORT( 0x008, IPRB, PORT_MRW, 0x0000, "Interrupt priority register B" )
1.108 + WORD_PORT( 0x00C, IPRC, PORT_MRW, 0x0000, "Interrupt priority register C" )
1.109 + WORD_PORT( 0x010, IPRD, PORT_MRW, 0xDA74, "Interrupt priority register D" )
1.110 +MMIO_REGION_END
1.111 +
1.112 +/* Timer unit (Page 277 [317] of sh7750h manual) */
1.113 +MMIO_REGION_BEGIN( 0xFFD80000, TMU, "Timer Unit" )
1.114 + BYTE_PORT( 0x000, TOCR, PORT_MRW, 0x00, "Timer output control register" )
1.115 + BYTE_PORT( 0x004, TSTR, PORT_MRW, 0x00, "Timer start register" )
1.116 + LONG_PORT( 0x008, TCOR0, PORT_MRW, 0xFFFFFFFF, "Timer constant 0" )
1.117 + LONG_PORT( 0x00C, TCNT0, PORT_MRW, 0xFFFFFFFF, "Timer counter 0" )
1.118 + WORD_PORT( 0x010, TCR0, PORT_MRW, 0x0000, "Timer control 0" )
1.119 + LONG_PORT( 0x014, TCOR1, PORT_MRW, 0xFFFFFFFF, "Timer constant 1" )
1.120 + LONG_PORT( 0x018, TCNT1, PORT_MRW, 0xFFFFFFFF, "Timer counter 1" )
1.121 + WORD_PORT( 0x01C, TCR1, PORT_MRW, 0x0000, "Timer control 1" )
1.122 + LONG_PORT( 0x020, TCOR2, PORT_MRW, 0xFFFFFFFF, "Timer constant 2" )
1.123 + LONG_PORT( 0x024, TCNT2, PORT_MRW, 0xFFFFFFFF, "Timer counter 2" )
1.124 + WORD_PORT( 0x028, TCR2, PORT_MRW, 0x0000, "Timer control 2" )
1.125 + LONG_PORT( 0x02C, TCPR2, PORT_R, UNDEFINED, "Input capture register" )
1.126 +MMIO_REGION_END
1.127 +
1.128 +/* Serial channel (page 541 [581] of sh7750h manual) */
1.129 +MMIO_REGION_BEGIN( 0xFFE00000, SCI, "Serial Communication Interface" )
1.130 + BYTE_PORT( 0x000, SCSMR1, PORT_MRW, 0x00, "Serial mode register" )
1.131 + BYTE_PORT( 0x004, SCBRR1, PORT_MRW, 0xFF, "Bit rate register" )
1.132 + BYTE_PORT( 0x008, SCSCR1, PORT_MRW, 0x00, "Serial control register" )
1.133 + BYTE_PORT( 0x00C, SCTDR1, PORT_MRW, 0xFF, "Transmit data register" )
1.134 + BYTE_PORT( 0x010, SCSSR1, PORT_MRW, 0x84, "Serial status register" )
1.135 + BYTE_PORT( 0x014, SCRDR1, PORT_R, 0x00, "Receive data register" )
1.136 + BYTE_PORT( 0x01C, SCSPTR1, PORT_MRW, 0x00, "Serial port register" )
1.137 +MMIO_REGION_END
1.138 +
1.139 +MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" )
1.140 + WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" )
1.141 +MMIO_REGION_END
1.142 +
1.143 +MMIO_REGION_LIST_BEGIN( sh4mmio )
1.144 + MMIO_REGION( MMU )
1.145 + MMIO_REGION( UBC )
1.146 + MMIO_REGION( BSC )
1.147 + MMIO_REGION( DMAC )
1.148 + MMIO_REGION( CPG )
1.149 + MMIO_REGION( RTC )
1.150 + MMIO_REGION( INTC )
1.151 + MMIO_REGION( TMU )
1.152 + MMIO_REGION( SCI )
1.153 + MMIO_REGION( SCIF )
1.154 +MMIO_REGION_LIST_END
1.155 +
1.156 +#endif
.