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lxdream.org :: lxdream/src/tst1.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/tst1.c
changeset 1:eea311cfd33e
author nkeynes
date Sat Mar 13 00:03:32 2004 +0000 (15 years ago)
permissions -rw-r--r--
last change This commit was generated by cvs2svn to compensate for changes in r2,
which included commits to RCS files with non-trunk default branches.
file annotate diff log raw
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/tst1.c Sat Mar 13 00:03:32 2004 +0000
1.3 @@ -0,0 +1,57 @@
1.4 +#include <stdint.h>
1.5 +
1.6 +#define PORT_R 1
1.7 +#define PORT_W 2
1.8 +#define PORT_MEM 4 /* store written value */
1.9 +#define PORT_RW 3
1.10 +#define PORT_MRW 7
1.11 +#define UNDEFINED 0
1.12 +
1.13 +struct mmio_region {
1.14 + char *id, *desc;
1.15 + uint32_t base;
1.16 + char *mem;
1.17 + struct mmio_port {
1.18 + char *id, *desc;
1.19 + int width;
1.20 + uint32_t offset;
1.21 + uint32_t default;
1.22 + int flags;
1.23 + } *ports;
1.24 +};
1.25 +
1.26 +#define _MACROIZE #define
1.27 +
1.28 +#define MMIO_REGION_BEGIN(b,id,d) struct mmio_region mmio_region_##id = { #id, d, b, NULL,
1.29 +#define LONG_PORT( o,id,f,def,d ) { #id, desc, 32, o, def, f }, \
1.30 +_MACROIZE port_##id o \
1.31 +_MACROIZE reg_##id (*(uint32_t *)(mmio_region_##id.mem + o))
1.32 +#define WORD_PORT( o,id,f,def,d ) { #id, desc, 16, o, def, f },
1.33 +#define BYTE_PORT( o,id,f,def,d ) { #id, desc, 8, o, def, f },
1.34 +#define MMIO_REGION_END {NULL, NULL, 0, 0, 0} };
1.35 +
1.36 +MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
1.37 + LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" ),
1.38 + LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" ),
1.39 +MMIO_REGION_END
1.40 +
1.41 +MMIO_REGION_BEGIN( BSC, 0xFF800000, "I/O Port Registers" )
1.42 + LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "" ),
1.43 + WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "" ),
1.44 + LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "" ),
1.45 + LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "" ),
1.46 + LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "" ),
1.47 + LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" ),
1.48 + WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" ),
1.49 + LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" ),
1.50 + WORD_PORT( 0x044, PCTRB, PORT_RW, UNDEFINED, "Port data register B" ),
1.51 + WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
1.52 +MMIO_REGION_END
1.53 +
1.54 +MMIO_REGION_BEGIN( SCI, 0xFFE00000, "Serial Controller Registers" )
1.55 +
1.56 +MMIO_REGION_END
1.57 +
1.58 +MMIO_REGIN_BEGIN( SCIF, 0xFFE80000, "Serial Controller (FIFO) Registers" )
1.59 +MMIO_REGION_END
1.60 +
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