1.1 --- a/src/sh4/mmu.c Tue Aug 19 13:00:46 2008 +0000
1.2 +++ b/src/sh4/mmu.c Tue Aug 19 22:58:05 2008 +0000
1.4 mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );
1.10 + WARN( "Performance counters not implemented" );
1.16 @@ -941,3 +947,19 @@
1.20 +/********************************* PMM *************************************/
1.23 + * Side note - this is here (rather than in sh4mmio.c) as the control registers
1.24 + * are part of the MMU block, and it seems simplest to keep it all together.
1.27 +int32_t mmio_region_PMM_read( uint32_t reg )
1.29 + return MMIO_READ( PMM, reg );
1.32 +void mmio_region_PMM_write( uint32_t reg, uint32_t val )