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lxdream.org :: lxdream/src/sh4/sh4mmio.h :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.h
changeset 819:ef4fec10a63a
prev818:2e08d8237d33
next826:69f2c9f1e608
author nkeynes
date Tue Aug 19 22:58:05 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Add stubs for the (undocumented) SH4 performance counter registers
file annotate diff log raw
1.1 --- a/src/sh4/sh4mmio.h Tue Aug 19 13:00:46 2008 +0000
1.2 +++ b/src/sh4/sh4mmio.h Tue Aug 19 22:58:05 2008 +0000
1.3 @@ -50,6 +50,16 @@
1.4 LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
1.5 LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
1.6 LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )
1.7 + WORD_PORT( 0x084, PMCR1, PORT_MRW, 0, "Performance counter control 1" )
1.8 + WORD_PORT( 0x088, PMCR2, PORT_MRW, 0, "Performance counter control 2" )
1.9 +MMIO_REGION_END
1.10 +
1.11 +/* Performance counter values (undocumented) */
1.12 +MMIO_REGION_BEGIN( 0xFF100000, PMM, "Performance monitoring" )
1.13 + LONG_PORT (0x004, PMCTR1H, PORT_MR, 0, "Performance counter 1 High" )
1.14 + LONG_PORT (0x008, PMCTR1L, PORT_MR, 0, "Performance counter 1 Low" )
1.15 + LONG_PORT (0x00C, PMCTR2H, PORT_MR, 0, "Performance counter 2 High" )
1.16 + LONG_PORT (0x010, PMCTR2L, PORT_MR, 0, "Performance counter 2 Low" )
1.17 MMIO_REGION_END
1.18
1.19 /* User Break Controller (Page 717 [757] of sh7750h manual) */
1.20 @@ -182,6 +192,7 @@
1.21 MMIO_REGION( TMU )
1.22 MMIO_REGION( SCI )
1.23 MMIO_REGION( SCIF )
1.24 + MMIO_REGION( PMM )
1.25 MMIO_REGION_LIST_END
1.26
1.27 /* mmucr register bits */
1.28 @@ -213,6 +224,11 @@
1.29 #define MEM_OC_INDEX0 (CCR_ORA|CCR_OCE)
1.30 #define MEM_OC_INDEX1 (CCR_ORA|CCR_OIX|CCR_OCE)
1.31
1.32 +#define PMCR_CLKF 0x0100
1.33 +#define PMCR_PMCLR 0x2000
1.34 +#define PMCR_PMST 0x4000
1.35 +#define PMCR_PMEN 0x8000
1.36 +
1.37 /* MMU functions */
1.38 void mmu_init(void);
1.39 void mmu_set_cache_mode( int );
.