lxdream 0.9.1| filename | src/sh4/sh4core.c |
| changeset | 732:f05753bbe723 |
| prev | 671:a530ea88eebd |
| next | 736:a02d1475ccfd |
| author | nkeynes |
| date | Thu Jul 10 01:46:00 2008 +0000 (14 years ago) |
| permissions | -rw-r--r-- |
| last change | Fix alignment check for 64-bit FMOVs Add missing MMU code etc to FMOV emu implementation |
| file | annotate | diff | log | raw |
1.1 --- a/src/sh4/sh4core.c Thu May 15 10:22:39 2008 +00001.2 +++ b/src/sh4/sh4core.c Thu Jul 10 01:46:00 2008 +00001.3 @@ -160,6 +160,18 @@1.4 #define TRACE_RETURN( source, dest )1.5 #endif1.7 +#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )1.8 +#define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )1.9 +#define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )1.10 +#define CHECKRALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )1.11 +#define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )1.12 +#define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )1.13 +#define CHECKWALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )1.14 +1.15 +#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }1.16 +#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }1.17 +#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)1.18 +1.19 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }1.20 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }1.21 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }1.22 @@ -169,48 +181,54 @@1.24 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)1.26 -#define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );1.27 -#define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );1.28 -1.29 -#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )1.30 -#define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )1.31 -#define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )1.32 -#define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )1.33 -#define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )1.34 -1.35 -#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }1.36 -#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }1.37 -#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)1.38 -1.39 -static void sh4_write_float( uint32_t addr, int reg )1.40 -{1.41 - if( IS_FPU_DOUBLESIZE() ) {1.42 - if( reg & 1 ) {1.43 - sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );1.44 - sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );1.45 - } else {1.46 - sh4_write_long( addr, *((uint32_t *)&FR(reg)) );1.47 - sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );1.48 - }1.49 - } else {1.50 - sh4_write_long( addr, *((uint32_t *)&FR((reg))) );1.51 +#define MEM_FP_READ( addr, reg ) \1.52 + if( IS_FPU_DOUBLESIZE() ) { \1.53 + CHECKRALIGN64(addr); \1.54 + memtmp = mmu_vma_to_phys_read(addr); \1.55 + if( memtmp == MMU_VMA_ERROR ) { \1.56 + return TRUE; \1.57 + } else { \1.58 + if( reg & 1 ) { \1.59 + *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(memtmp); \1.60 + *((uint32_t *)&XF(reg)) = sh4_read_long(memtmp+4); \1.61 + } else { \1.62 + *((uint32_t *)&FR(reg)) = sh4_read_long(memtmp); \1.63 + *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(memtmp+4); \1.64 + } \1.65 + } \1.66 + } else { \1.67 + CHECKRALIGN32(addr); \1.68 + memtmp = mmu_vma_to_phys_read(addr); \1.69 + if( memtmp == MMU_VMA_ERROR ) { \1.70 + return TRUE; \1.71 + } else { \1.72 + *((uint32_t *)&FR(reg)) = sh4_read_long(memtmp); \1.73 + } \1.74 }1.75 -}1.76 -1.77 -static void sh4_read_float( uint32_t addr, int reg )1.78 -{1.79 - if( IS_FPU_DOUBLESIZE() ) {1.80 - if( reg & 1 ) {1.81 - *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);1.82 - *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);1.83 - } else {1.84 - *((uint32_t *)&FR(reg)) = sh4_read_long(addr);1.85 - *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);1.86 - }1.87 - } else {1.88 - *((uint32_t *)&FR(reg)) = sh4_read_long(addr);1.89 +#define MEM_FP_WRITE( addr, reg ) \1.90 + if( IS_FPU_DOUBLESIZE() ) { \1.91 + CHECKWALIGN64(addr); \1.92 + memtmp = mmu_vma_to_phys_write(addr); \1.93 + if( memtmp == MMU_VMA_ERROR ) { \1.94 + return TRUE; \1.95 + } else { \1.96 + if( reg & 1 ) { \1.97 + sh4_write_long( memtmp, *((uint32_t *)&XF((reg)&0x0E)) ); \1.98 + sh4_write_long( memtmp+4, *((uint32_t *)&XF(reg)) ); \1.99 + } else { \1.100 + sh4_write_long( memtmp, *((uint32_t *)&FR(reg)) ); \1.101 + sh4_write_long( memtmp+4, *((uint32_t *)&FR((reg)|0x01)) ); \1.102 + } \1.103 + } \1.104 + } else { \1.105 + CHECKWALIGN32(addr); \1.106 + memtmp = mmu_vma_to_phys_write(addr); \1.107 + if( memtmp == MMU_VMA_ERROR ) { \1.108 + return TRUE; \1.109 + } else { \1.110 + sh4_write_long( memtmp, *((uint32_t *)&FR((reg))) ); \1.111 + } \1.112 }1.113 -}1.115 gboolean sh4_execute_instruction( void )1.116 {
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